Fishing – trapping – and vermin destroying
Patent
1994-03-15
1995-02-28
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 90, 437162, 437 89, 437915, H01L 21265
Patent
active
053936817
ABSTRACT:
A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.
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Fitch Jon T.
Mazure Carlos A.
Witek Keith E.
Hearn Brian E.
Motorola Inc.
Nguyen Tuan
Witek Keith E.
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