Method for forming a chip package

Details Method for forming a chip package Method for forming a chip package

2007-08-07

2007-08-07

Tugbang, A. Dexter (Department: 3729)

Textiles: manufacturing

Warp preparing or handling

Machine replenishing

C029S832000, C029S835000, C029S838000, C029S846000, C257S666000, C438S123000

Reexamination Certificate

active

10918911

ABSTRACT:
A chip package is formed which has an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another to permit a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggered in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.

REFERENCES:
patent: 3795044 (1974-03-01), Peltz
patent: 5221428 (1993-06-01), Ohsawa et al.
patent: 6355502 (2002-03-01), Kang et al.
patent: 6576496 (2003-06-01), Bolken et al.

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