Method for forming a capacitor with electrically interconnected

Details Method for forming a capacitor with electrically interconnected Method for forming a capacitor with electrically interconnected

1995-05-17

1997-08-05

Tsai, Jey

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

438396, 438397, H01L 2170, H01L 2700

Patent

active

056542224

ABSTRACT:
A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing an electrically conductive first layer over the node; c) providing an electrically insulative barrier second layer over the first conductive layer; d) providing a third layer over the electrically insulative barrier layer, the third layer comprising a material which is either electrically conductive and resistant to oxidation, or forms an electrically conductive material upon oxidation; e) providing an insulating inorganic metal oxide dielectric layer over the electrically conductive third layer; f) providing an electrically conductive fourth layer over the insulating inorganic metal oxide dielectric layer; and g) providing an electrically conductive interconnect to extend over the second insulative layer and electrically interconnect the first and third conductive layers. A capacitor construction having such a dielectric layer in combination with the barrier layer and electrical interconnect of a first capacitor plate is disclosed.

REFERENCES:
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5102820 (1992-04-01), Chiba
Onishi, Shigeo et al., "A Half-Micron Ferroelectric Memory Cell Technology with Stacked Capacitor Structure", IEEE, 1994, pp. 843-846.
Lesaicherre, P-Y et al., "A Gbit-Scale DRAM Stacked Technology With ECR MOCVD SrTiO.sub.3 and RIE Patterned RuO.sub.2 /TiN Storage Node", IEEE, 1994, pp. 831-834.
Eimori, T. et al., "A Newly Designed Planar Stacked Capacitor Cell With High Dielectric Constant Film for 256Mbit DRAM", IEEE, 1993, pp. 631-634.

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