Method for forming a capacitor in dram

Semiconductor device manufacturing: process – Making passive device – Stacked capacitor

Reexamination Certificate

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Reexamination Certificate

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06326276

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor capacitor, and more particularly to a method for forming a cylindrical capacitor in a dynamic random access memory (DRAM) cell.
2. Description of the Prior Art
Demand for dynamic random access memories (DRAMs) has rapidly increased owing to widespread use of integrated circuits. An integral part of a DRAM is storage capacitors, one of which is associated with each bit of information that is to be stored and/or read. These capacitors have typical capacity values, which allow them to be formed in situ together with other components such diodes and transistors. In order to minimize the amount of real estate occupied by the capacitors it has become routine to depart from a simple flat plate geometry and to give them a three dimensional aspect such as a hollow cylinder.
Further, in order to adapt the trend of reducing dimensions of semiconductor devices, sub-micron technologies were widely spread today. In the fabrication of capacitors in a DRAM cell, conventional masks are commonly used for photolithography processes, for example, to define the pattern on photoresist. After exposure, the unnecessary portion of the photoresist is stripped away, the residual portion then serves an etching mask which facilitates the subsequent etch process for forming capacitors. But in the sub-micron process (especially in the process for 0.18 &mgr;m or less critical dimension), the conventional masks have very high prices leading to increasing the cost of fabrication for DRAM.
For the reason mentioned above, there is a need to develop a method that can reduce the number of masks used to fabricate DRAM. Moreover, the cost of fabrication will be reduced, too.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming capacitors. It substantially reduces the number of mask and the cost of fabrication for DRAM. In one embodiment, It's illustrated to form a hollow cylindrical capacitor. Firstly, a solid cylindrical conductor on a first dielectric layer is provided, then a second dielectric layer is formed on the solid cylindrical conductor. Next, a polysilicon layer is formed on the second dielectric layer, wherein a portion of the second dielectric layer is exposed. The etch process is used to etch the second dielectric layer till top surface of the solid cylindrical conductor is exposed; after removing the polysilicon layer, the solid cylindrical conductor is etched. After removing the second dielectric layer, the hollow cylindrical capacitor is achieved.


REFERENCES:
patent: 5668039 (1997-09-01), Lin
patent: 5811332 (1998-09-01), Chao
patent: 6093601 (2000-07-01), Tsai et al.

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