Method for forming a capacitor in a semiconductor device

Details Method for forming a capacitor in a semiconductor device Method for forming a capacitor in a semiconductor device

2000-05-25

2001-10-23

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000, C438S396000

Reexamination Certificate

active

06306667

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor memory exemplified by a DRAM (dynamic random access memory), and more specifically to a method for forming a capacitor in the semiconductor memory.
With an increased integration density of the semiconductor memory exemplified by a DRAM, it is actively researched to form a capacitor insulating film of a high dielectric constant insulating material typified by (Ba, Sr)TiO
3
, in place of a silicon oxide and a silicon nitride.
Referring to
FIGS. 1A
to
1
C, there are shown diagrammatic sectional views for illustrating a process for forming a capacitor having a high dielectric constant insulating film in a semiconductor memory.
FIG. 1A
shows a condition that a lower electrode
103
is formed on an interlayer insulator film
102
at a position of a capacitor contact
101
formed to penetrate through the interlayer insulator film
102
. This lower electrode
103
can he formed by depositing a multilayer metal film formed of Ti, TiN and Ru on the interlayer insulator film
102
by a sputtering, and by patterning the multilayer metal film into a desired shape by a dry etching using a patterned photoresist mask.
As shown in
FIG. 1B
, a high dielectric constant insulating film
104
of (Ba, Sr)TiO
3
is formed to cover the whole surface by a MO-CVD (metal organic chemical vapor deposition) process, and an upper electrode
105
of Ru (ruthenium) is formed on the high dielectric constant insulating film
104
by a sputtering.
Thereafter, as shown in
FIG. 1C
, an interlayer insulator film
106
is formed to cover the whole surface by a CVD process, so that an interconnection will he formed on the interlayer insulator film
106
.
In the above mentioned example, if the interlayer insulator film
106
is formed of a NSG (non-doped silicate glass) film which is formed by a CVD process using TEOS (tetraethoxysilane) as a starting material, the interlayer insulator film
106
becomes uneven over the whole surface, as shown in FIG.
1
C. The cause for this is considered that the NSG film formed by the CVD process using the TEOS as the starting material is apt to be influenced by crystallinity and hydration of an underlying layer, with the result that if the crystallinity and the hydration of the underlying layer is not satisfactory, it is difficult to form an uniform NSG film. In addition, in a stepped structure created by the patterned lower electrode
103
as shown in
FIG. 1B
, it is difficult to control a crystallographic axis at an upper surface and at a side surface of the electrode (because an orientation axis of a deposited film becomes perpendicular to the substrate and therefore the crystallographic axis at the upper surface of the electrode becomes perpendicular to the crystallographic axis at the side surface of the electrode), with the result that the grown NSG film has an irregular film thickness over the whole surface.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for fabricating a semiconductor memory, which has overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a method for forming in the semiconductor memory a capacitor covered with an interlayer insulator film formed of an NSG film which is formed by a CVD process using the TEOS and which has an uniform thickness.
The above and other objects of the present invention are achieved in accordance with the present invention by a method for forming a capacitor in the semiconductor memory, the method comprising the steps of forming a lower electrode having a desired pattern on an insulating film, forming a high dielectric constant insulating film to cover the whole surface including the lower electrode, forming an upper electrode layer to cover the high dielectric constant insulating film, performing a plasma treatment to expose a surface of the upper electrode layer to plasma, and depositing a non-doped silicate glass (NSG) film to cover the upper electrode layer by a CVD process using tetraethoxysilane (TEOS) as a starting material.
For example, the plasma treatment is carried out by exposing a surface of the upper electrode layer to plasma of an O
2
gas to a mixed gas of Ar/Cl
2
(90%/10% in volume)
With the above mentioned arrangement, since the surface of the upper electrode layer is treated with plasma, the surface of the upper electrode layer is subjected to damage at some degree, so that homology the surface has a some degree of roughness. In other words, nucleuses (or defects) from which a crystal grows, are uniformly generated over the whole surface by the plasma treatment. Thus, a suctorial layer is uniformly formed at the whole surface of the upper electrode layer, so that the NSG film formed by a CVD process using the TEOS as a starting material can be grown to have a uniform film thickness.
As mentioned hereinbefore, in the stepped structure created by the patterned lower electrode, it was difficult to control a crystallographic axis at an upper surface and at a side surface of the electrode, with the result that the grown NSG becomes greatly irregular in film thickness over the whole surface. In the present invention, however, since the suctorial layer is uniformly formed at the whole surface of the upper electrode layer by treating the surface of the upper electrode layer with plasma, the NSG film formed by a CVD process using the TEOS as a starting material can be grown to have a uniform film thickness.
In addition, even in a structure patterned to be difficult to control a crystallographic axis, since nucleuses are uniformly generated over the whole surface by the plasma treatment, an uniform film can be formed.
On the other hand, when the NSG film is formed to cover the upper electrode layer by the CVD process using the TEOS as the starting material without treating the surface of the upper electrode layer by plasma, it was difficult to form an uniform NSG film because the NSG film formed by the CVD process using the TEOS as the starting material is easily influenced by crystallinity aid hydration of an underlying layer.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.


REFERENCES:
patent: 6001660 (1999-12-01), Park et al.
patent: 6127218 (2000-10-01), Kang
patent: 6143598 (2000-11-01), Martin et al.
patent: 6150689 (2000-11-01), Narui et al.

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