Method for forming a capacitor for semiconductor devices...

Details Method for forming a capacitor for semiconductor devices... Method for forming a capacitor for semiconductor devices...

2001-01-02

2002-11-12

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S253000, C438S255000, C438S240000

Reexamination Certificate

active

06479364

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a capacitor for semiconductor devices, and more particularly, to a method for forming a capacitor for highly integrated semiconductor devices, in which a TaON layer having a large dielectric constant is used as a dielectric layer.
2. Description of the Related Art
Recently, as the degree of integration of semiconductor devices has increased, the unit cell area decreased remarkably. As a result, manufacturing a capacitor having sufficient capacitance for such highly integrated semiconductor devices has become increasingly more difficult. In particular, in DRAM designs having one MOS transistor and one capacitor, the word lines and bit lines are arranged in a perpendicular relationship to one another over a semiconductor substrate, and the capacitor extends over two gates that are separated by a contact hole. In such arrangements, the capacitor occupies a large portion of the chip and includes a polysilicon layer as a conductive layer and an oxide layer, a nitride oxide (NO) layer, or an oxide-nitride-oxide (ONO) layer as a dielectric layer. In manufacturing highly integrated DRAMs, reducing the cell area of the capacitor while achieving high capacitance values becomes a critical design factor.
As known, capacitance (C) is expressed as C=(∈
0
×∈
r
×A)/T, where ∈
0
is vacuum permitivity, ∈
r
is the dielectric constant of the dielectric layer, A is the surface area of the capacitor, and T is the thickness of the dielectric layer. As can be inferred from the expression, the capacitance can be increased by using a material having a large dielectric constant to form the dielectric layer, reducing the thickness of the dielectric layer, or increasing the surface area of the dielectric layer. However, each of these methods for increasing capacitance has problems associated with the respective method.
In particular, although there has been an active research into dielectric materials having a large dielectric constant—such as tantalum oxide (Ta
2
O
5
), titanium oxide (TiO
2
) or BST SrTiO
3
—the properties of these dielectric materials have not been sufficiently verified. For example, the effect of the dielectric materials on the reliability of devices in terms of the junction breakdown voltage and on the properties of the thin dielectric layer itself is unclear. Accordingly, it is difficult to utilize such dielectric materials in actual semiconductor device manufacturing processes.
On the other hand, reducing the thickness of the dielectric layer may cause the dielectric layer to punch through during operation, thereby lowering the reliability of the capacitor.
For 256 megabytes or greater DRAMs, a TaON layer—whose dielectric constant is 3-4 times larger than the conventional SiON layer that has a dielectric constant of about 7—has been suggested for use as the dielectric layer. However, the TaON layer raises a problem in actual manufacturing processes. During the deposition of the TaON layer and a subsequent thermal process, the TaON layer reacts with a polysilicon layer serving as a storage electrode, and as a result, a parasitic capacitor of SiO
2
is formed at the interface between the TaON layer and the storage electrode, which lower the overall capacitance value of the capacitor.
In particular, when a TaON layer is deposited by chemical vapor deposition (CVD) using Ta(O(C
2
H
5
)
2
)
5
as a source material, and O
2
as a reaction gas, a polysilicon layer serving as a storage electrode is oxidized by oxygen originating from the source and reaction gases. Furthermore, oxygen is activated during subsequent low-temperature plasma treatment in a N
2
O atmosphere and during a high-temperature thermal process performed at about 600° C. to 800° C. for about
1
hour. The oxidation reaction of the storage electrode is facilitated by the activated oxygen, thereby resulting in a SiO
2
layer having a small dielectric constant between the storage electrode and the TaON layer.
The presence of the SiO
2
layer lowers the capacitance of the resultant semiconductor device. If no such intermediate layer exists between the TaON layer and the storage electrode, the total capacitance (C
tot
) is equal to the capacitance (C
TaON
) of the TaON layer. If an intermediate dielectric layer exists, the total capacitance C
tot
is dependent upon the dielectric constant (∈
intermediate
) and the thickness (d
intermediate
) of the intermediate dielectric layer. This is expressed as:
C
tot
=(
C
TaON
×C
intermediate
)/(
C
TaON
+C
intermediate
), where
C
intermediate
=∈
intermediate
/d
intermediate
.
FIG. 1
illustrates a capacitor for semiconductor devices manufactured according to a conventional method. As shown in
FIG. 1
, an oxide layer for isolation (not shown) and a gate oxide layer (not shown) are formed over a semiconductor substrate
41
. Next, a MOS field effect transistor, which consists of a gate electrode (not shown) and source/drain electrodes (not shown) and bit lines (not shown) are formed. Then an interlayer dielectric (ILD) film
43
for planarization is deposited over the semiconductor substrate
41
.
Following this, a photosensitive pattern (not shown) is formed on the ILD film
43
, such that a portion of the ILD film
43
, which serves as a storage electrode contact in conjunction with the source or drain electrode, is exposed. The ILD film
43
is etched using the photosensitive pattern as an etching mask to form a storage electrode contact hole. The photosensitive pattern is removed and a conductive layer (not shown) is deposited over the semiconductor substrate
41
, filling the storage electrode contact hole. A core insulation layer (not shown) is formed over the conductive layer, and a storage electrode mask is formed on a portion of the core insulation layer aligned with a future storage electrode. The conductive layer and the core insulation layer are etched using the storage electrode mask as an etching mask, thereby resulting in a core insulation pattern (not shown) and a storage electrode
45
.
Next, a conductive layer for spacer is deposited over the semiconductor substrate
41
, and then etched to form a spacer
47
on the sidewalls of the storage electrode
45
, so that a cylindrical storage electrode is completed. Then, the core insulation pattern is removed. A hemispherical silicate glass (HSG) layer
49
is optionally formed on the storage electrode
45
and the spacer
47
to increase the surface area of the storage electrode
45
.
Next, a SiN layer
50
as a diffusion barrier is formed over the semiconductor substrate
41
, and a TaON layer
51
as a dielectric layer is deposited over the SiN layer
50
. A TiN layer
53
as a diffusion barrier and a plate electrode
55
are formed in succession, thereby resulting in a complete capacitor.
As previously mentioned, in such conventional method of forming a capacitor, to suppress a reduction in the total capacitance, the SiN layer having a thickness of 50 Å is formed as a diffusion barrier, such that diffusion of oxygen into the storage electrode, i.e., a lower electrode, can be prevented. However, such a thin SiN layer having a thickness of 50 Å cannot effectively block the diffusion of oxygen, and thus a SiO
2
layer is still formed between the lower electrode and the SiN layer.
On the other hand, when a high-temperature process is performed on the TaON layer that is formed as the dielectric layer for a denser structure, TaON is crystallized into Ta
2
O
5
and nitrogen diffuses out of the dielectric layer. As a result, the number of free Ta atoms in the dielectric layer, from which oxygen is separated, increases, thereby deteriorating dielectric characteristics of the TaON layer. In addition, free Ta atoms serve as electron traps that cause leakage current, thereby degrading the properties of the capacitor.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a method for formi

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