Etching a substrate: processes – Forming or treating electrical conductor article – Forming or treating of groove or through hole
Patent
1994-10-06
1995-08-01
Powell, William
Etching a substrate: processes
Forming or treating electrical conductor article
Forming or treating of groove or through hole
437189, 437194, 216 38, 216 48, 216 47, 216 80, B44C 122, C03C 1500, C23F 102
Patent
active
054377633
ABSTRACT:
A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit. A second masking layer having openings which define the locations of the contact vias to be created is then formed over the second insulating layer. The size of the openings in the second masking layer are smaller than the size of the openings in the first masking layer. The contact vias are then formed through the first and second insulating layers.
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patent: 4946550 (1990-08-01), Van Laarhoven
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Hill Kenneth C.
Jorgenson Lisa K.
Powell William
Robinson Richard K.
SGS-Thomson Microelectronics Inc.
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