Method for formation of a stacked capacitor

Details Method for formation of a stacked capacitor Method for formation of a stacked capacitor

1990-11-07

1991-09-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437228, 437233, 437235, 437919, H01L 2170

Patent

active

050495178

ABSTRACT:
A method is disclosed for forming a capacitor on a semiconductor wafer which utilizes top and back sides of a capacitor node for capacitance maximization. First and second dielectric layers, having different etch rates, are applied atop the wafer, and a contact opening is etched therethrough. Poly is applied and etched to begin formation of one node of the capacitor. A layer of oxide is then formed atop the poly capacitor node. The first dielectric layer is then etched, leaving a projecting or floating capacitor node which is surrounded by the second dielectric material and oxide formed thereatop. The surrounding material is then etched, the capacitor dielectric applied, and the poly of the second capacitor nod applied and selectively etched.

REFERENCES:
patent: 4953126 (1990-08-01), Ema
patent: 5021357 (1991-06-01), Taguchi et al.
T. Ema et al., "3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMS", IEDM Tech. Digest, pp. 592, 595, 1988.
S. Inoue et al., "A Spread Stacked Capacitor (SSC) Cell For 64MBIT DRAMS", IEDM Tech. Digest, pp. 31-34, 1989.

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