Method for flattening hierarchical design descriptions

Details Method for flattening hierarchical design descriptions Method for flattening hierarchical design descriptions

1991-06-12

1995-12-05

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

054735467

ABSTRACT:
The invention describes a method for expanding (flattening) hierarchical descriptions of electronic circuits into flat descriptions. The method is characterized by two processes: one which eliminates feed-through and implicit signals, and another which pre-plans the layout of the flattened data structure before flattening. The flattening process may then take advantage of a number of resulting efficiencies to operate more quickly than present flatteners.

REFERENCES:
patent: 4635208 (1987-01-01), Coleby et al.
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patent: 5034899 (1991-07-01), Schult
patent: 5084824 (1992-01-01), Lam et al.
patent: 5111413 (1992-05-01), Lazansky et al.
patent: 5164908 (1992-11-01), Igarashi
patent: 5164911 (1992-11-01), Juran et al.
"IDEAS-An Integrated Design Automation System" by Z. Mehmood et al., 1987 IEEE International Conference on Computer Design: VLSI in Computers & Processors, Oct. 5-8, 1987, pp. 407-412.
"Circuit Compilers Dont't Have To Be Slow" by William C. Diss, 25th ACM/IEEE Design Automation Conference, IEEE 1987, pp. 622-627.

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