Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-03-03
2004-04-06
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S437000, C438S697000, C438S705000
Reexamination Certificate
active
06716720
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for filling a depression between two vertically adjoining semiconductor layers, in particular for filling edge depressions that form during a lateral isolation of adjacent transistors or other active regions by using trenches that are etched into the semiconductor substrate and filled with an insulating material.
Planar technology is usually used during the lateral patterning of semiconductor wafers in the context of forming integrated circuits. Planar technology includes a sequence of individual processes which each act on the whole area of the wafer surface and, by using suitable masking layers, lead to the local alteration of the semiconductor material in a targeted manner. During the lateral patterning of a semiconductor wafer, the procedure is usually such that trenches are etched into the semiconductor substrate using a mask layer and are then filled with a corresponding material. In particular when filling narrow trenches, the filling material is deposited in a large-area manner and is subsequently removed as far as the wafer surface by using a removal process, thereby producing essentially a plane surface over the entire semiconductor wafer. However, during this removal process, depressions usually arise in the edge region of the plane surface at the transition between the semiconductor layers that are arranged vertically one beside the other. The depressions principally arise due to the fact that, during the process of filling the trenches, stresses are produced at the interfaces between the semiconductor layers and, during the subsequent removal process and subsequent etching processes, these stresses lead to increased rates of removal and etching rates, respectively, in this boundary region, as a result of which depressions form at the transition between the vertical semiconductor layers.
Such edge depressions also arise, in particular, during the formation of trench isolations for laterally isolating closely adjacent active regions in the context of very large scale integration technology. In trench isolation technology, the procedure is such that trenches are etched into the semiconductor substrate between the active regions, e.g. using a nitride mask, and, after a short thermal oxidation, oxide is deposited conformally in order to fill the trenches and the surface is subsequently uncovered by etching back the deposited oxide layer or by chemical mechanical polishing. This method makes it possible to produce field oxides in very narrow interspaces having a width of less than 100 nm. However, at the edge between the field oxide trenches and the active regions, depressions often arise during the etching-back or chemical mechanical polishing process, which depressions can lead to undesirable electrical effects in the integrated circuit formed on the semiconductor wafer.
There is thus the risk that, during the subsequent production of gate layers for forming field-effect transistors on the active regions, short circuits to the adjacent transistor can occur on account of gate material residues which remain during the process sequence. Furthermore, in the depressions, parasitic transistors with a low threshold voltage may form in the edge region of the gate electrodes, so-called “corner devices” which lead to increased leakage currents. In order to avoid depressions in the edge region between the field oxide trenches and the active regions, an elevated field oxide level compared with the active regions is therefore produced in the trench regions in the context of the etching-back or chemical mechanical polishing processes. However, the resulting step leads to an impaired conformity of the subsequent coating on account of the step being covered incompletely, as a result of which the electrical function of the deposited layer is adversely effected. In particular when fabricating extremely small structures, it is necessary, therefore, to fabricate essentially plane surfaces for the coating processes.
An article by T. Ogura et al. “A Shallow Trench Isolation with SiN Guard-Ring for Sub-Quarter Micron CMOS Technologies” presents a trench isolation technique in which the field oxide filling is surrounded by a guard ring made of SiN in order to fill edge depressions and, at the same time, to avoid the risk of corner devices arising. However, the production of an SiN guard ring requires an additional expensive lithography process sequence and, moreover, additionally presupposes a minimum step height.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for filling depressions between two vertically adjoining semiconductor layers, in particular, edge depressions that form in the context of trench isolation technology, which overcomes the above-mentioned disadvantages of the prior art methods of this general type.
It is an object of the invention to provide a method that can be used to fill such depressions in a simple manner whilst avoiding steps at the edges.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for filling a depression between two vertically adjoining semiconductor layers. The method includes: forming two vertically adjoining semiconductor layers on a semiconductor wafer, the two semiconductor layers being made of different materials and an edge depression forming near a transition between the two semiconductor layers; in a large-area manner, applying an essentially uniform covering layer having a predetermined layer thickness above the two semiconductor layers to cover the two semiconductor layers and the edge depression lying between the two semiconductor layers; increasing a rate at which the covering layer can be subsequently removed by introducing a doping material into the covering layer essentially down to a depth corresponding to the layer thickness of the covering layer; and removing the covering layer with the doping material such that undoped covering layer material remains in the edge depression.
In accordance with an added feature of the invention, the covering layer is provided as an electrically neutral material.
In accordance with an additional feature of the invention, an electrically neutral material is used as the doping material.
In accordance with another feature of the invention, the step of introducing the doping material into the covering layer loosens a structure of the covering layer.
In accordance with a further feature of the invention, the material of one of the two semiconductor layers is used as material for the covering layer.
In accordance with a further added feature of the invention, the step of forming the two semiconductor layers is performed by: patterning a mask layer on the semiconductor wafer to define a trench region; forming a trench in the semiconductor wafer; in a large-area manner, applying an oxide layer to fill the trench; removing the oxide layer to uncover the mask layer; and removing the mask layer.
In accordance with a further additional feature of the invention, the step of applying the covering layer includes forming an oxide layer as the covering layer.
In accordance with yet an added feature of the invention, nitrogen is used as the doping material.
In accordance with yet an additional feature of the invention, the oxide layer has a layer thickness of approximately 25 nm and the nitrogen is implanted with an energy of 8 keV.
According to the invention, in order to fill a depression which forms between two vertically adjoining semiconductor layers made of different materials, an essentially uniform covering layer having a predetermined layer thickness is applied in a large-area manner over the two semiconductor layers to cover the depression. A doping material is then introduced into the covering layer, essentially down to a depth that corresponds to the layer thickness. The doping material provides for an increased rate of removal of the covering layer. Afterward, the covering layer with the doping material is then removed. The inve
Efferenn Dirk
Moll Hans-Peter
Fourson George
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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