Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-07-22
2001-01-30
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185050, C365S185160, C365S185020
Reexamination Certificate
active
06181604
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to generally to semiconductor memory devices and, more particularly, to a method for programming EPROMS and multi-level Flash EPROMS.
2. Description of the Related Art
Erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM) and Flash memory are classes of floating gate memory devices. More particularly, these floating gate memory devices are programmable memory devices which use floating gates as charge storage layers. These devices are based on a memory transistor, consisting of a source, channel, and a drain with a floating gate over the channel and a control gate isolated from the floating gate. Programming a cell requires charging the floating gate with electrons, which increases the turn on threshold of the memory cell. Flash EPROMS typically use a “hot electron” programming technique to charge the cells. When programmed, the cell will not turn on, i.e. it remains non-conductive, if a read potential is applied to its control gate. To erase the cell, electrons are removed from the floating gate in order to lower the threshold. With a lower threshold, the cell will now turn on when a read potential is applied to the control gate.
Conventionally, hot electron programming is performed by ramping up the drain voltage or the gate voltage. In other words, the source voltage is first shorted to ground, and then the drain (or gate) voltage is increased. Finally, the gate (or drain) voltage is applied. One programming method which operates by varying the gate voltage has been disclosed in U.S. Pat. No. 5,563,822, the disclosure of which is hereby incorporated by reference. However, this programming method has low programming efficiency and a large leakage current is induced by the drain-turn-on or punch-through problems of the unselect cells. Two proposals to overcome these problems include U.S. Pat. No. 5,553,020, disclosing a programming method that applies a source bias, and U.S. Pat. No. 5,590,076, disclosing a constant current source programming method.
More recently, memory cells have included multiple levels in order to provide more data storage. For instance, instead of having only two threshold states, a larger number of threshold states are now being used and sensed as separate data levels. This allows for increased data storage for a given amount of memory. The addition of multiple levels increases the programming problems associated with the prior art solutions, since multiple levels are already more difficult to program.
In the view of the foregoing, there is a need for faster and more efficient schemes for programming erasable programmable memory cells, especially for multi-level Flash EPROMS.
SUMMARY OF THE INVENTION
The present invention is a method for programming a semiconductor memory device, which combines the advantages of ramping down a source voltage with the advantages associated with increasing a gate voltage. A programming period is divided into a program disturbance inhibited period and a program period. During a program disturbance inhibited period, a ground line GL is first pulled high, then a data line DL is pulled up, and finally a word line WL voltage is pulled up. Under these conditions, the data line DL and the ground line GL are kept at a high voltage to inhibit programming during this period. In addition, the corresponding BWL and DWL/DWR lines are turned on to prevent any voltages from disturbing the adjacent cells during the following programming period.
During the programming period, the ground line GL is pulled down and the corresponding BWL line is turned on to generate a high electric field between the drain and the source of the programmed cell, in order to perform hot electron programming. A programming method performed by ramping down the source bias is thereby achieved.
In a second embodiment, the programming period is further divided into sub-program periods, with each sub-program period having a program disturbance and a program period. The wordline WL voltage may increase with each sub-program period to improve the programming speed. Also, the program disturbance period may only be performed for the first sub-program period.
In another embodiment, each sub-program period may also include a verify period, in order to implement a program and verify technique suitable for programming multi-level Flash EPROMS.
The programming method of the present invention is thus able to combine the advantages associated with ramping down a source voltage with the advantages associated with increasing a gate voltage. The programming method is also especially suited for programming virtual ground EPROM devices.
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Lin Chin Hsi
Lu Tao Cheng
Ni Ful Long
Tsai Wen Jer
Wang Mam Tsung
Beyer Weaver & Thomas LLP
Elms Richard
Macronix International Co. Ltd.
Nguyen Hien
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