Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-06-25
2001-01-09
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180
Reexamination Certificate
active
06172913
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for fast programming floating gate memory cells by tunnel effect, wherein the term “programming” means the injection or extraction of charges from the floating gate of the cells by the Fowler-Nordheim effect.
BACKGROUND OF THE INVENTION
Memory cells of the EEPROM and flash (fully Fowler-Nordheim) type are programmed by tunnel effect, which can render programming slow for reasons of reliability. Typically, this operation requires a few milliseconds, i.e., a much longer time than the duration of the clock pulses used in current digital electronic circuits. This slowness constitutes a disadvantage for the use of this type of memory, such as ROMs (Read Only Memories of the programmable and erasable types), and prevents them from being used as read and write devices (RAM—Random Access Memory).
For RAM applications, another important parameter is represented by the memory endurance, i.e., the maximum number of programming cycles that the memory is able to withstand (before it ceases being programmable within the times and according to the modalities specified). RAM memories normally have to be written and erased a far higher number of times than ROMs (although of the programmable type).
On the other hand, the programming time (T
pr
) for floating gate cells is inversely proportional to the current used for injecting or extracting electrons into or from the floating gate, which, in the case where the tunnel effect is employed, exponentially depends upon the electric field (F
ox
) applied to the oxide region that separates the floating gate region from the conducting regions of the cell. It is thus evident that an increase (although modest) of this electric field makes it possible to substantially increase the programming current, until the programming times are reduced to values similar to those normally used for RAM memories (typically, around 100 ns or lower).
At present, however, it is not considered feasible to increase the electric field applied during programming in that it is generally believed that its increase would seriously jeopardize the reliability of the tunnel oxide. In fact, it is known that the application of a strong electric field to the insulating oxide layers produces irreversible changes in the electrical properties of the insulating layers themselves; in particular, the phenomenon of greatest interest, referred to as SILC (Stress Induced Leakage Current), determines an increase in the conductivity of the insulating layer when low value electric fields are applied, thus giving rise to leakages which can jeopardize data retention of the floating gate cells.
In detail, it is known that the SILC phenomenon increases as the applied electric field (F
ox
) and the programming time (T
pr
) increase. On the other hand, since in programming floating gate memory cells it is necessary to discuss in terms of a given amount of charge being transferred from or to the floating gate, F
ox
and T
pr
necessarily vary inversely with respect to one another; i.e., the increase of one entails the reduction of the other. Consequently, as regards the SILC resulting from programming operations for which a strong electric field is to be used to reduce the programming time substantially, it is essential to know whether the negative effect due to the increase in the field prevails or not over the positive effect induced by the reduction in the programming time.
Currently, it is generally believed that the negative effect prevails and that an increase in the electric field with respect to the currently adopted values(on the order of 8 MV/cm) leads to unsatisfactory reliability features. This belief is based on the results of experiments carried out with programming times T
pr
of up to 1 &mgr;s which have actually shown that the oxide decay increases as the programming electric field increases.
SUMMARY OF THE INVENTION
The present invention provides a fast programming method, whereby the level of oxide decay may be zero or negligible.
In accordance with the invention, a floating gate memory is provided that enables a fast programming method of floating gate memory cells by tunnel effect.
Based upon studies carried out by the inventor, it has been shown that, given the same transferred charge, the behavior of SILC is not monotonic and that decay, in fact, increases as the programming time decreases (with consequent increase in the electric field) up to a certain value (that is, in the range of values so far explored, from which it is difficult to increase the value of the programming electric field without definitively degrading the memory cell), and then starts decreasing.
From the physical standpoint, the decrease in the decay of the oxide layer as the programming time decreases (with simultaneous increase in the electric field applied) is probably due to the characteristic times of formation of permanent decay which is not an instantaneous phenomenon, since it requires modification of a lattice type. Consequently, by programming the memory cells with voltage pulses shorter than or comparable with these characteristic times, decay is inhibited.
In particular, the study of the phenomena linked to fast programming on devices that are widely representative of the state of the art indicates that the values of the programming times at which the reversal of the trend occurs are within the region of a few dozen nanoseconds, and hence within the range of the typical operation times of modern integrated circuits.
Consequently, with programming times lower than or equal to 100 ns and electric fields on the tunnel oxide layer greater than or equal to 10 MV/cm, it is possible to program floating gate memory cells and prevent the SILC phenomenon from arising to an appreciable extent.
REFERENCES:
patent: 5901084 (1999-05-01), Ohnakado
patent: 5986931 (1999-11-01), Caywood
patent: 6009017 (1999-12-01), Gus et al.
patent: 6011287 (2000-01-01), Itoh et al.
Ricco, B. and A. Pieracci, “Tunneling Bursts for Negligible SILC Degradation,”IEEE Transactions on Electron Devices, 46(7):1497-1500, 1999.
Galanthay Theodore E.
Le Vu A.
Seed IP Law Group
STMicroelectronics S.r.l.
Tarleton E. Russell
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