Method for failure analysis of megachips using scan techniques

Details Method for failure analysis of megachips using scan techniques Method for failure analysis of megachips using scan techniques

1994-01-12

1996-08-27

Beausoliel, Jr., Robert W.

Excavating

371 223, 324532, G01R 3128, G06F 1130

Patent

active

055508413

ABSTRACT:
Testing of a semiconductor integrated circuit is conducted by determining all paths leading to a failed location on a chip. Potentially faulty locations are then determined by finding faults which occurred at the same time the failing vector was scanned, and the intersection of the paths and the faulty locations form a smaller set of potentially faulty locations on the IC. Further testing of the nodes which are in this smaller set is performed until a single location or small portion of a chip may be visually inspected with little effort.

REFERENCES:
patent: 5291495 (1994-03-01), Udell
patent: 5331570 (1994-07-01), Bershteyn
patent: 5430736 (1995-07-01), Takeoka et al.
LSI Logic, Chip-Level Full Scan Design Methodology Guide, Jan. 1992, pp. ii-D11.

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