Method for facilitating engineering changes in a multiple level

Metal working – Method of mechanical manufacture – Electrical device making

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29846, H05K 302

Patent

active

061017108

ABSTRACT:
An anticipation of engineering changes to a multiple-level integrated circuit package, resulting in a significant decrease in the turnaround time required to make engineering changes. After the first pass of the design phase is complete and before manufacture has begun, surplus I/O at different package levels are wired into surplus connections involving all but the highest package level. These surplus connections are reserved for future use when engineering changes become necessary. Once manufacture is complete, the surplus connections can be converted into logical connections by ECing only the highest packaging level with the quickest turnaround time. The surplus connections also provide a means for implementing ongoing incremental engineering changes as they are needed.

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patent: 5184284 (1993-02-01), Ashelin et al.
patent: 5360767 (1994-11-01), Narayanan et al.
IBM Technical Disclosure Bulletin "Silicon Elevated, Wireless Module Method For Making Engineering Changes" vol. 31 No. 10 pp. 71-74, Mar. 1989.
IBM Technical Disclosure Bulletin, "Verification and Implementation of Post-Manufacturing Chip Design Change" by T.A. Bellwood, et al., vol. 36, No. 07, Jul. 1993, pp. 27-31.
IBM Technical Disclosure Bulletin, "Spare I/O Preparation for Use at Release Interface Tape B" by J.J. Sanders, et al., vol. 34, No. 10A, Mar. 1992, pp. 186-190.

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