Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Patent
1989-12-08
1999-11-23
Quach, T. N.
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
438485, 438600, H01L 2128
Patent
active
059899433
ABSTRACT:
In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.
REFERENCES:
patent: 3611063 (1971-10-01), Neale
patent: 3619732 (1971-11-01), Neale
patent: 3629863 (1971-12-01), Neale
patent: 3634927 (1972-01-01), Neale et al.
patent: 3675090 (1972-07-01), Neale
patent: 3677814 (1972-07-01), Gillery
patent: 3699543 (1972-10-01), Neale
patent: 3775174 (1973-11-01), Neale
patent: 3792319 (1974-02-01), Tsang
patent: 4174521 (1979-11-01), Neale
patent: 4199692 (1980-04-01), Neale
patent: 4217374 (1980-08-01), Ovshinsky et al.
patent: 4225946 (1980-09-01), Neale et al.
patent: 4226898 (1980-10-01), Ovshinsky et al.
patent: 4228524 (1980-10-01), Neale et al.
patent: 4312046 (1982-01-01), Taylor
patent: 4431271 (1984-02-01), Okubo
patent: 4442507 (1984-04-01), Roesner
patent: 4458297 (1984-07-01), Stopper et al.
patent: 4467400 (1984-08-01), Stopper
patent: 4479088 (1984-10-01), Stopper
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4517223 (1985-05-01), Oushinsky et al.
patent: 4545111 (1985-10-01), Johnson
patent: 4569121 (1986-02-01), Lim et al.
patent: 4599705 (1986-07-01), Holmberg et al.
patent: 4621260 (1986-11-01), Suzuki et al.
patent: 4651409 (1987-03-01), Ellsworth et al.
patent: 4726851 (1988-02-01), Matsumura et al.
patent: 4771015 (1988-09-01), Kanai et al.
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 4866006 (1989-09-01), Imagawa et al.
patent: 4882293 (1989-11-01), Naumann et al.
patent: 4914055 (1990-04-01), Gordon et al.
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5181096 (1993-01-01), Forouhi
patent: 5502315 (1996-03-01), Chua et al.
Bogdan, Albert A., "An electrically Programmable Silicon Circuit Board", Mosaic Systems, Inc., pp. 472-476 (no date provided).
Cole, B., "ICC Takes the Antifuse One Step Further", Electronics, Mar. 1989, p. 87.
Cole, B., "Programmable Logic Devices: Faster, Denser, and a Lot More of Them", Electronics, Sep. 17, 198, pp. 61-72.
Gordon, K. and Wong, R., "Conducting Filament of the Programmed Metal Electrode Amorphous Silicon Antifuse", IEDM 93 (Dec. 1993) pp. 27-30.
Iversen, W., "Amorphous.vias in wafer link chips", Electronics, vol. 56, No. 19, Sep. 22, 1983, pp. 48-49.
Iversen, W., "Amorphous switches add PROM density", Electronics, vol. 57, No. 7, Apr. 5, 1984,,p. 54.
Millman, J. and Halkias, C., Integrated Electronics: Analog And Digital Circuits And Systems, McGraw-Hill Book Company, New York, 1972, pp. 58-59.
Raffel, J., et al., "Laser Programmed Vias for Restructurable VLSI", Massachusetts Institute of Technology, Lincoln Laboratory, International Electron Devices Meeting, 1980, pp. 132-135.
Raffel, J., et al., "A Demonstration of Very Large Area Integration Using Restructurable Laser Links", Massachusetts Institute of Technology, Lincoln Laboratory, IEEE ISSCC 1982, 9 pages.
Raffel, J., et al., "A Demonstration of Very Large Area Integration Using Laser Restructuring", IEEE International Symposium on Circuits and Systems, vol. 2, May 1983, pp. 781-784.
Raffel, J., et al., "A Wafer-Scale Digital Integrator", IEEE International Conference on Computer Designs VLSI in Computers, Oct. 1984, pp. 121-126.
Wyatt, P., et al., "Process Considerations in Restructurable VLSI for Wafer-Scale Integration", Massachusetts Institute of Technology, Lincoln Laboratory, International Electron Devices Meeting, Dec. 1984, pp. 626-629.
"Rad-Hard Verticle Anti-Fuse Technology Reduces IC Geometry", Defense Electronics, vol. 26, No. 5, May 1994, p. 12.
A.C. Adams, "Plasma Deposition of Inorganic Films," Solid State Technology,/Apr. 1983, pp. 135-139.
Burns et al., "Application of plasma-deposited SiN to wafer-scale integrated circuits," IEEE Transations or Electron Devices, vol. ED-34, No. 11, Nov. 1987, pp. 2374-2375.
B. Cook et al., "Amorphous Silicon antifuse technology for bipolar Proms," Bipolar Circuits and Technology Meeting, pp. 99-100.
K. El-Ayat et al., "A CMOS electrically configurable gate array," IEEE International Solid State Circuits Conference, 1988, pp. 76-77.
E. Hamdy et al., "Dielectric based antifuse for logic and memory Ics," IEMD, 1988, pp. 786-789.
J.C. Knights et al., "Microstructure of plasma-deposited a-Si:H films," Appl. Phys. Lett. vol. 35, No. 3, Aug. 1,1979, pp. 244-246.
D. L. Morel, et al., "Effect of hydrogen on the diode properties of reactively sputtered amorphous silicon Schottky barrier structures," Appl. Phys. Lett., vol. 39, No. 8, Oct. 15, 1981, pp. 612-3.
Y. Shacham-Diamond et al., "A novel ion-implanted amorphous silicon programmable element," IEDM, 1987, pp. 194-197.
H. Stopper, "A wafer with electrically programmable interconnections," IEEE International Solid State Circuits Conference, 1985, pp. 268-269.
Vossen and Kern, Thin Film Processes, Academic Press, 1978.
Chittick, et al., "The Preparation and Properties of . . . ", J. Electrochem. Soc., vol. 116, No. 1, Jan. 1969, pp. 77-81.
Wolf, et al., Silicon Processing, Lattice Press, 1986, vol. I, pp. 280-283.
Bechtel Richard L.
Birkner John M.
Chan Andrew K.
Chua Hua-Thye
Thomas Mammen
Quach T. N.
QuickLogic Corporation
LandOfFree
Method for fabrication of programmable interconnect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabrication of programmable interconnect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabrication of programmable interconnect structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1221039