Method for fabrication of monolithic integrated circuits

Details Method for fabrication of monolithic integrated circuits Method for fabrication of monolithic integrated circuits

1987-04-20

1988-12-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

148DIG14, 148DIG21, 156652, 156656, 156662, 430316, 357 51, 357 41, 437 59, 437 60, 437177, 437184, 437192, 437195, 437912, 437919, 437926, H01L 2948, H01L 21283

Patent

active

047896450

ABSTRACT:
During fabrication of monolithic microwave integrated circuits, active devices having sources, gates, drains, and/or Schottky barrier junctions are first provided for an epitaxial layers. Then many layers of metals and oxides are produced thereover in situ without removing the circuit from its environmental chamber. Circuit elements are then defined by processing of the many layers sequentially by photolithography and other processes from the top of the chip downward. Certain combinations of metals, oxides, and processes are selected to enable fabrication of circuits from the top down in this way. This reduces inclusion of contaminating chemical films and particles between the desired layers. Lumped and distributed capacitors, resistors, inductors, transmission lines, contacts, and complete active devices are monolithically defined, with a reduced number of process steps. An all-refractory MESFET is described, having a Schottky barrier gate and nonalloyed ohmic contacts for source and drain producible at room temperatures. Source, gate, and drain can be defined with a single mask. A thinner gold layer is formed for FET contacts than for other circuit conductors and elements by means of a configured tantalum layer buried in a thick gold layer.

REFERENCES:
patent: 3808041 (1974-04-01), Rosenberger et al.
patent: 3900944 (1975-08-01), Fuller et al.
patent: 4179533 (1979-12-01), Christou et al.
patent: 4236829 (1980-12-01), Chikamura et al.
patent: 4301233 (1981-11-01), Calviello
patent: 4310570 (1982-01-01), Calviello
patent: 4312112 (1982-01-01), Calviello
patent: 4316201 (1982-02-01), Christou et al.
patent: 4319258 (1982-03-01), Harnagel et al.
patent: 4325073 (1982-04-01), Hughes et al.
patent: 4325181 (1982-04-01), Yoder
patent: 4381595 (1983-05-01), Denda et al.
patent: 4471005 (1984-09-01), Cheng et al.
patent: 4514751 (1985-04-01), Bhattacharya
patent: 4519127 (1985-05-01), Arai
patent: 4534099 (1985-08-01), Howe
patent: 4617724 (1986-10-01), Yokoyama et al.
Calviello et al., "Quasi-Monolithic . . . ", Microwave Journal, May 1986, pp. 243-258.
Calviello et al., "First Successful Fabrication of High-Performance All-Refractory-Metal, (Ta-Au) GaAs FET. . . ", Electronics Letters, May 8, 1986, vol. 22, No. 10, pp. 510-512.
Meier et al., "Integrated Ka-Band Front End with Monolithic Mixer", abstract only, 1985, IEEE MTT-S International Microwave Symposium, pp. 151-154.
Tsaur et al., "Molecular Beam Epitaxy of GaAs and AlGaAs on Si", Appl. Phys. Lett. 45(5), Sep. 1, 1984, pp. 535-536.

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