Method for fabrication of enlarged stacked capacitors using...

Details Method for fabrication of enlarged stacked capacitors using... Method for fabrication of enlarged stacked capacitors using...

1999-08-16

2001-09-25

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S253000, C438S255000, C438S622000, C257S306000, C257S309000

Reexamination Certificate

active

06294436

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to semiconductor memory fabrication and more particularly, to a method for fabricating enlarged stacked capacitors by employing isotropic etching.
2. Description of the Related Art
Semiconductor memory cells include capacitors accessed by transistors to store data. Data is stored as a high or low bit depending on the state of the capacitor cell. The capacitor's charge or lack of charge indicates a high or low when accessed to read data, and the capacitor is charged or discharged to write data from the capacitor through a bit-line sense amplifier circuit.
Stacked capacitors are among the types of capacitors used in semiconductor memories, for example, dynamic random access memories (DRAM). Stacked capacitors are typically located on top of the cell transistor used to access a storage node of the capacitor as opposed to trench capacitors which are buried in the substrate of the device. Higher cell capacitance is beneficial for improving data sensing margin in DRAM devices.
In semiconductor memories, such as dynamic random access memories (DRAM) which include stacked capacitors, an area for a memory cell is proportional to the size of a stacked capacitor. For sub-8F
2
stacked capacitor DRAMs, i.e., DRAMs with memory cells occupying an area of less than 8F
2
where F is a minium feature size of a given technology, the projected area of capacitor is drastically decreased. For example, only 1F
2
of area for a 4F
2
cell is available for the stacked capacitor and only 2F
2
of area for a 6F
2
cell is available for the stacked capacitor, while 3F
2
of area is available for the stacked capacitor in a 8F
2
cell. Thus, cell capacitance is also drastically decreased with the decrease minimum feature size (F) and also the decrease of cells in a layout.
Referring to
FIG. 1
, a layout for 8F
2
memory cells each having a stacked capacitor is shown. In the layout, stacked capacitors
10
are disposed in rows and columns. Active areas
12
are shown between pairs of stacked capacitors
10
. Active areas
12
are surrounded by shallow trench isolation regions
14
.
Referring to
FIG. 2
, a cross-sectional view is shown taken at section line
2
—
2
of FIG.
1
.
FIG. 2
illustratively depicts the major elements of the 8F
2
memory cells. Stacked capacitors
10
are shown having a top electrode
16
, a bottom electrode
18
and a capacitor dielectric layer
20
therebetween. Bottom electrode
18
is connected to a plug
22
which extends down to a portion of active area
12
. Active areas
12
form an access transistor for charging and discharging stacked capacitor
10
in accordance with data on a bitline
24
. Bitline
24
is coupled to a portion of active area
12
(source or drain of the access transistor) by a contact
23
. When a gate conductor
28
is activated the access transistor conducts and charges or discharges stacked capacitor
10
. When F is reduced with each new generation of DRAM design, stacked capacitor
12
loses area thereby reducing the capacitors capabilities. A typical capacitor area for an 8F
2
memory cell is equal to about 3F
2
.
Referring to
FIG. 3
, a layout for 6F
2
memory cells each having a stacked capacitor is shown. In the layout, stacked capacitors
30
are disposed in rows and columns. Active areas
32
are shown between pairs of stacked capacitors
30
, similar to FIG.
1
. Active areas
32
are surrounded by narrower shallow trench isolation regions
34
.
Referring to
FIG. 4
, a cross-sectional view is shown taken at section line
4
—
4
of FIG.
3
.
FIG. 4
illustratively depicts the major elements of the 6F
2
memory cells. Stacked capacitors
30
are shown having a top electrode
36
, a bottom electrode
38
and a capacitor dielectric layer
40
therebetween. Bottom electrode
38
is connected to a plug
42
which extends down to a portion of active area
32
. Active areas
32
form an access transistor for charging and discharging stacked capacitor
30
in accordance with data on a bitline
44
. Bitline
44
is coupled to a portion of active area
32
(source or drain of the access transistor) by a contact
43
. When a gate conductor
48
is activated the access transistor conducts and charges or discharges stacked capacitor
30
. Stacked capacitors
30
are smaller than those of the 8F
2
memory cells. When F is reduced with each new generation of DRAM design, stacked capacitor
30
losses area thereby reducing the capacitors capabilities. A typical capacitor area for a 6F
2
memory cell is equal to about 2F
2
.
Therefore, a need exists for a method for increasing or maintaining stacked capacitor area while reducing the size of memory cells.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for expanding holes for the formation of stacked capacitors includes the steps of providing a planarized dielectric layer for forming bottom electrodes of the stacked capacitors, forming a first dielectric layer on the planarized dielectric layer, forming a second dielectric layer on the first dielectric layer, the second dielectric layer being selectively etchable relative to the first dielectric layer, etching the second dielectric layer to form holes for forming the bottom electrodes and isotropically etching the second dielectric layer to expand the holes for forming the bottom electrodes.
A method for forming stacked capacitors for a semiconductor memory device, in accordance with the present invention, includes the steps of providing a substrate having a planarized dielectric layer formed on access transistors, the planarized dielectric layer having conductive plugs disposed therein for connecting to the access transistors, forming a first dielectric layer on a top surface of the planarized dielectric layer, forming a second dielectric layer which is selectively etchable relative to the first dielectric layer, patterning holes in the second dielectric layer by selectively etching the second dielectric layer relative to the first dielectric layer and isotropically etching the holes in the second dielectric layer to expand the holes to provide an increased surface area within the holes over a surface area formed by the selectively etching the second dielectric layer.
Another method for forming stacked capacitors for a dynamic random access memory device includes the steps of
providing a substrate having a planarized glass layer formed on access transistors, the planarized glass layer having conductive plugs disposed therein for connecting to the access transistors, forming a nitride layer on a top surface of the planarized glass layer, forming an oxide layer which is selectively etchable relative to the nitride layer, depositing a resist layer on the oxide layer, patterning the resist layer by forming openings in the resist over locations for the conductive plugs, anisotropically etching holes in the oxide layer by selectively etching the oxide layer relative to the nitride layer, isotropically etching the holes in the oxide layer to expand the holes to provide an increased surface area within the holes over a surface area formed by the selectively etching the oxide layer, removing the resist layer, removing portions of the nitride layer in the holes to expose the conductive plugs, depositing a conductive layer in the holes to form a bottom electrode for the stacked capacitors, and depositing a capacitor dielectric layer on the conductive layer.
In alternate methods, the first dielectric layer may include a nitride (or aluminum oxide) and the second dielectric layer may include an oxide. The steps of removing portions of the first dielectric layer in the holes, depositing a conductive layer in the holes to form the bottom electrode and depositing a capacitor dielectric layer on the conductive layer are preferably included. The step of isotropically etching may include employing wet etching or chemical dry etching. The wet etch process may employ HF, diluted HF or BHF. The chemical dry etching may include CF
4
—O
2
, C
2
F
6
, CH
4
—I
2
(Br
2
, Cl
2
), CH
4
—Br
2
(Cl
2

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