Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2011-04-11
2011-11-15
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S197000, C438S455000, C257SE21023, C257SE21598
Reexamination Certificate
active
08058137
ABSTRACT:
A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks in a first direction and at least one of the second alignment marks in a second direction.
REFERENCES:
patent: 4711858 (1987-12-01), Harder et al.
patent: 5312771 (1994-05-01), Yonehara
patent: 6020263 (2000-02-01), Shih et al.
patent: 6281102 (2001-08-01), Cao et al.
patent: 6294018 (2001-09-01), Hamm et al.
patent: 6321134 (2001-11-01), Henley et al.
patent: 6353492 (2002-03-01), McClelland et al.
patent: 6759282 (2004-07-01), Campbell et al.
patent: 7052941 (2006-05-01), Lee
patent: 7141853 (2006-11-01), Campbell et al.
patent: 7166520 (2007-01-01), Henley
patent: 7205204 (2007-04-01), Ogawa et al.
patent: 7223612 (2007-05-01), Sarma
patent: 7378702 (2008-05-01), Lee
patent: 7436027 (2008-10-01), Ogawa et al.
patent: 7459752 (2008-12-01), Doris et al.
patent: 7470142 (2008-12-01), Lee
patent: 7470598 (2008-12-01), Lee
patent: 7488980 (2009-02-01), Takafuji et al.
patent: 7508034 (2009-03-01), Takafuji et al.
patent: 7633162 (2009-12-01), Lee
patent: 7671371 (2010-03-01), Lee
patent: 7960242 (2011-06-01), Or-Bach et al.
patent: 2006/0024923 (2006-02-01), Sarma et al.
patent: 2007/0108523 (2007-05-01), Ogawa et al.
patent: 2007/0275520 (2007-11-01), Suzuki
patent: 2008/0038902 (2008-02-01), Lee
patent: 2008/0160431 (2008-07-01), Scott et al.
patent: 2008/0160726 (2008-07-01), Lim et al.
patent: 2009/0224364 (2009-09-01), Oh et al.
patent: 2009/0325343 (2009-12-01), Lee
patent: 2010/0038743 (2010-02-01), Lee
Chen, P. et al., “Effects of Hydrogen Implantation Damage on the Performance of InP/InGaAs/InP p-i-n Photodiodes, Transferred on Silicon,” Applied Physics Letters, Jan. 2009, pp. 012101-1 to 012101-3, vol. 94, No. 1.
Lee, D. et al., “Single-Crystalline Silicon Micromirrors Actuated by Self-Aligned Vertical Electrostatic Combdrives with Piston-Motion and Rotation Capability,” Sensors and Actuators A114, 2004, pp. 423-428.
Shi, X. et al., “Characterization of Low-Temperature Processed Single-Crystalline Silicon Thin-Film Transistor on Glass,” IEEE Electron Device Letters, Sep. 2003, pp. 574-576, vol. 24, No. 9.
Chen, W. et al., “InP Layer Transfer with Masked Implantation,” Electrochemical and Solid-State Letters, Apr. 2009, H149-150, Issue 12, No. 4.
Motoyoshi, M., “3D-IC Integration,” 3rd Stanford and Tohoku University Joint Open Workshop, Dec. 4, 2009, pp. 1-52.
Weis, M. et al., “Stacked 3-Dimensional 6T SRAM Cell with Independent Double Gate Transistors,” IC Design and Technology, May 18-20, 2009.
Feng, J. et al., “Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate,” IEEE Electron Device Letters, Nov. 2006, pp. 911-913, vol. 27, No. 11.
Zhang, S., “Stacked CMOS Technology on SOI Substrate,” IEEE Electron Device Letters, Sep. 2004, pp. 661-663, vol. 25, No. 9.
Topol, A.W. et al., “Enabling SOI-Based Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs),” IEDM Tech. Digest, Dec. 5, 2005, p. 363-366.
Batude, P. et al., “Advances in 3D CMOS Sequential Integration,” 2009 IEEE International Electron Devices Meeting (Baltimore, Maryland), Dec. 7-9, 2009, pp. 14.1.1-14.1.4.
Tan, C.S. et al., “Wafer Level 3-D ICs Process Technology,” ISBN-10: 0387765328, Springer, 1st Ed., Sep. 19, 2008, pp. v-xii, 34, 58, and 59.
Mistry, K., “A 45nm Logic Technology With High-K+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-Free Packaging,” Electron Devices Meeting, 2007, IEDM 2007, IEEE International, Dec. 10-12, 2007, p. 247.
Srivastava, P. et al., “Silicon Substrate Removal of GaN DHFETs for enhanced (>1100V) Breakdown Voltage,” Aug. 2010, IEEE Electron Device Letters, vol. 31, No. 8, pp. 851-852.
Celler, G.K. et al., “Frontiers of silicon-on-insulator,” J. App. Phys., May 1, 2003, pp. 4955-4978, vol. 93, No. 9.
Henttinen, K. et al., “Mechanically Induced Si Layer Transfer in Hydrogen-Implanted Si Wafers,” Applied Physics Letters, Apr. 24, 2000, p. 2370-2372, vol. 76, No. 17.
Beinglass Israel
Cronquist Brian
de Jong Jan Lodewijk
Or-Bach Zvi
Sekar Deepak C.
Ghyka Alexander
Monolithic 3D Inc.
Sartori Michael A.
Venable LLP
Wang Yao
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