Method for fabrication of a semiconductor device

Details Method for fabrication of a semiconductor device Method for fabrication of a semiconductor device

1999-01-11

2001-10-30

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

Reexamination Certificate

active

06309948

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to improvements in integrated circuit processing, and more particularly, to minimizing damage to previously defined isolation structures and semiconductor surfaces during subsequent device processing steps.
Device isolation typically is achieved by utilizing local oxidation of silicon (“LOCOS”) or shallow trench isolation (“STI”) techniques. In the STI device isolation technique, isolation commonly is provided by forming a recess or trench between two active area mesas, upon which the electronic devices are located and filling the trench with an insulating material. Shallow trench isolation serves to provide higher packing density, improved isolation and greater planarity, by avoiding the topographical irregularities encountered when using conventional thick film oxide isolation (LOCOS). Typically, trench isolation technology includes a planarization process to remove oxide from the active area mesas and maintain oxide in the trenches.
Several techniques have been developed for planarization of wafer surfaces as part of trench isolation processing. These techniques are well known and have been disclosed in U.S. Pat. Nos. 5,492,858; 5,498,565; and 5,290,396.
FIG. 1
shows an active area mesa
16
formed on a semiconductor substrate
12
and isolated from surrounding semiconductor areas by insulating oxide
14
deposited in isolation trench
13
and insulating material
15
deposited in isolation trench
17
. As shown in
FIG. 1
, surface
20
of substrate
12
is substantially planar with surfaces
18
and
19
of insulating materials
14
and
15
, respectively. As previously explained, the process of planarization to remove insulating material from the surface of active area mesas and to maintain the material in the trenches is well known in the art.
Referring now to
FIG. 2
, a gate electrode
30
is formed on active area mesa
16
and is surrounded by spacer oxide
32
. As known in the art, the surrounding semiconductor material is doped
26
as desired. Once spacer oxide
32
has been formed, the device may be processed to create a silicide layer
21
over the exposed semiconductor surfaces.
As shown in
FIG. 2
, a problem with the processing techniques of the prior art is that when defining device structures after planarization, particularly spacers
32
positioned adjacent to gate electrode
30
, surface
20
of the semiconductor substrate may be damaged by the etchants used to form such structures. Damage to the semiconductor surface
20
may cause poor silicide formation
28
and result in decreased device performance. In addition to damage to the semiconductor surface, a portion of the insulating material
14
and
15
filling trenches
13
and
17
, respectively, may also be lost during the etching process. After completion of device processing, the surfaces
18
and
19
of insulating oxide
14
and
15
, respectively, are substantially spaced from surface
20
. Surfaces
18
and
19
have been reduced from their previous positions by distance
22
and
23
, respectively, and are below the level of doping
26
and silicide
21
. Loss of insulating material
14
and
15
in isolating trenches
13
and
17
, respectively, may result in junction leakage, causing poor device performance.
Therefore, there remains a need for a convenient and cost-effective process to protect the surface of the substrate and the insulating material in place in the isolation trenches during subsequent device processing steps.
SUMMARY OF THE INVENTION
The present invention contemplates a method for forming a semiconductor structure on an active area mesa with a minimal loss of an insulation material deposited in an isolation trench adjacent the mesa. The method comprises defining a plurality of isolation trenches in a semiconductor substrate to define at least one active area mesa and filling the trenches with an insulating material. A gate electrode is formed on the active area mesa. An etch barrier material is deposited over at least the isolation material to protect it during subsequent processing steps. The etch barrier material may be extended over the semiconductor surface to protect it during subsequent etching steps. Device processing is completed by depositing additional material and etching the material with a selective etch to form integrated circuit structures. The selective etching having the ability to etch one or more of the additional materials at a rate higher than it etches the etch barrier material. Once the desired structures have been formed, an etchant having a selectivity for the etch barrier material is applied to expose the underlying structures.
One object of the present invention is to protect the insulating material in the isolation trenches from damage during subsequent device processing steps.
Another object of the present invention is to protect the surface of the semiconductor substrate during subsequent device processing steps.
Still another object of the invention is to provide a method for making integrated circuit devices having improved yield and performance.
These and other objects of the present invention will become apparent based upon the following description.


REFERENCES:
patent: 3013467 (1961-12-01), Minsky
patent: 4869781 (1989-09-01), Euen et al.
patent: 4956314 (1990-09-01), Tam et al.
patent: 5034613 (1991-07-01), Denk et al.
patent: 5091652 (1992-02-01), Mathies et al.
patent: 5130268 (1992-07-01), Liou et al.
patent: 5173439 (1992-12-01), Dash et al.
patent: 5192980 (1993-03-01), Dixon et al.
patent: 5210435 (1993-05-01), Roth et al.
patent: 5290396 (1994-03-01), Schoenborn et al.
patent: 5296703 (1994-03-01), Tsien
patent: 5358891 (1994-10-01), Tsang et al.
patent: 5374585 (1994-12-01), Smith et al.
patent: 5385861 (1995-01-01), Bashir et al.
patent: 5447884 (1995-09-01), Fahey et al.
patent: 5472905 (1995-12-01), Paek et al.
patent: 5474953 (1995-12-01), Shimizu et al.
patent: 5480832 (1996-01-01), Miura et al.
patent: 5492858 (1996-02-01), Bose et al.
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5516625 (1996-05-01), McNamara et al.
patent: 5567553 (1996-10-01), Hsu et al.
patent: 5622596 (1997-04-01), Armacost
patent: 5681771 (1997-10-01), Hwang
patent: 5723370 (1998-03-01), Ning et al.
patent: 5751417 (1998-05-01), Uhl
patent: 5785651 (1998-07-01), Kuhn et al.
patent: 5866465 (1999-02-01), Doan

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