Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-05-22
1999-03-09
Bowers, Charles
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438156, 438173, 438294, 438296, H01L 2184
Patent
active
058800069
ABSTRACT:
A method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. The trench insulating material is protected by an etch barrier layer having at least a partial resistance to etchants used in further device processing steps. The barrier layer may also be deposited over the surface of the substrate to protect it from damage during device processing. The barrier layer may be removed by an etchant having a selectivity for the barrier layer over that of the surrounding device elements. Final processing of the device may be completed once the barrier layer is removed.
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Harvey Ian R.
Lee Henry
Lin Xi-Wei
Blum David S.
Bowers Charles
VLSI Technology Inc.
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