Fishing – trapping – and vermin destroying
Patent
1996-07-17
1997-09-30
Niebling, John
Fishing, trapping, and vermin destroying
437 41, 437186, H01L 21265, H01L 2144
Patent
active
056725310
ABSTRACT:
A method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, the method includes providing a semiconductor substrate having a gate insulator and a gate electrode, the gate electrode having opposing first and second sidewalls defining the length of the gate electrode and a top surface. Lightly doped source and drain regions are implanted into the semiconductor substrate and are substantially aligned with the sidewalls of the gate electrode. After implanting the lightly doped regions, first and second spacers are formed adjacent to the first and second sidewalls of the gate electrode. After forming the spacers, a portion of the gate electrode is removed to form a third sidewall of the gate electrode opposite the second sidewall, thereby eliminating the first sidewall and reducing the length of the gate electrode. After removing the first spacer, heavily doped source and drain regions are implanted into the semiconductor substrate. The heavily doped drain region is substantially aligned with the outer edge of the second spacer, a portion of the lightly doped drain region is protected beneath the second spacer, and the heavily doped source region is substantially aligned with the third sidewall. In another embodiment, the heavily doped drain region is implanted after the spacers are formed but before the third sidewall is formed and the heavily doped source region is implanted after forming the third sidewall.
REFERENCES:
patent: 4272881 (1981-06-01), Angle
patent: 5200358 (1993-04-01), Bollinger et al.
patent: 5286664 (1994-02-01), Horiuchi
patent: 5296398 (1994-03-01), Noda
patent: 5424229 (1995-06-01), Oyamatsu
patent: 5525552 (1996-06-01), Huang
patent: 5547885 (1996-08-01), Ogoh
Duane Michael P.
Gardner Mark I.
Wristers Derick J.
Advanced Micro Devices , Inc.
Lebentritt Michael S.
Niebling John
Sigmond David M.
Tsirigotis M. Kathryn
LandOfFree
Method for fabrication of a non-symmetrical transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabrication of a non-symmetrical transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabrication of a non-symmetrical transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2256298