Method for fabrication of a MOS transistor

Semiconductor device manufacturing: process – Forming schottky junction – Using refractory group metal

Reexamination Certificate

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Details

C438S575000, C438S576000, C257S412000, C257S610000

Reexamination Certificate

active

07470605

ABSTRACT:
Disclosed is a method for fabricating a MOS transistor. The present method includes the steps of: (a) forming a gate electrode including a gate insulating layer and a polysilicon gate conductive layer on an active region in a semiconductor substrate; (b) forming a metal layer over the substrate including the gate electrode; (c) heat-treating the substrate to form a polycide layer on a top surface and sidewalls of the gate electrode; (d) removing an unreacted portion of the metal layer; (e) removing the polycide layer from the top surface and sidewalls of the gate electrode, thus reducing a width of the gate electrode; and (f) forming source and drain regions in the active region adjacent to the gate electrode.

REFERENCES:
patent: 6072222 (2000-06-01), Nistler
patent: 2004/0224450 (2004-11-01), Itonaga et al.

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