Method for fabricating wafer-scale integration wafers and method

Details Method for fabricating wafer-scale integration wafers and method Method for fabricating wafer-scale integration wafers and method

1992-06-30

1993-05-25

Atkinson, Charles E.

Excavating

371 151, 365200, 437 51, 437 52, 257202, G06F 1110

Patent

active

052146570

ABSTRACT:
The invention relates primarily to wafer-scale integration. Yet in one aspect, circuitry is provided to enable dicing of the wafer to use discrete memory sections thereon as memory chips should the wafer as a whole fail test. In another aspect, error detection and correction circuitry is provided within the street area to detect and correct errors generated within the discrete memory sections where wafer-scale integration manufacturing is successful. In another aspect, clusters of discrete sections of integrated circuitry are provided which include RAM integrated circuitry. One discrete section within the cluster comprises a) control circuitry to control and coordinate operation of discrete sections within the cluster, and b) error detection and correction circuitry to detect and correct errors generated within the discrete sections of RAM integrated circuitry. In still another aspect, test circuitry including fuses are provided within the street area and interconnect with selective portions of different discrete sections of circuitry. Fuses within the test circuitry would be provided and selectively blown to isolate the inoperative areas from each respective memory section, thereby effectively increasing the yield of operable circuitry on the wafer.

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