Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-01-05
2001-11-20
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S297000, C438S425000, C438S439000
Reexamination Certificate
active
06319795
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to processes for fabricating very-large-scale integrated (VLSI) circuits, and in particular to a new process for forming line-width-independent self-aligned trench isolations that separate VLSI circuit elements.
2. Description of the Prior Art
Semiconductor devices are constantly being miniaturized. As both the overall dimensions of semiconductor devices and the lithographic line widths for making such devices are made smaller and smaller hundreds of thousands of integrated circuit (IC) elements such as metal-oxide-semiconductor field-effect transistors (MOSFETs) are formed within each square centimeter of a semiconductor substrate surface. To prevent these elements from short-circuiting or electronically interfering with one another, isolation regions must be formed at the surface of the substrate to define and separate each of the regions where the IC elements are to be formed. Conventional art for forming such isolation regions include, for example, the use of the local oxidation of silicon (LOCOS) process to form field oxide (FOX) regions, and the shallow trench isolation (STI) process, both of which are well-known to those skilled in the art.
As an example of the current state of the conventional art,
FIGS. 1A-1G
depict various stages of a process that combines the features of LOCOS and STI to form isolation regions on a semiconductor substrate. As shown in
FIG. 1A
, a pad oxide (e.g., silicon oxide) layer
12
and a pad nitride (e.g., silicon nitride) layer
14
are sequentially formed on a semiconductor substrate
10
. Conventional lithographic and etching techniques are used to remove portions of the pad nitride
14
and the pad oxide
12
, exposing a plurality of surface areas of the substrate. Each such surface area defines an active region
16
.
Next, a thin polysilicon (poly-Si) layer
18
is deposited on the substrate, covering the pad nitride layers
14
as well as the active regions
16
. Silicon nitride side walls
20
are then formed on portions of the active region
16
and next to the side walls of the poly-Si-coated pad nitride layers
14
, leaving the central portion of the active region
16
covered only by the poly-Si layer
18
.
Next, as shown in
FIG. 1B
, through a thermal oxidation process, a field oxide region
22
, partly inset in the substrate
10
, is formed at the central portion of the active region
16
. The exposed portions of poly-Si
18
′ located at the top of the pad nitride are also oxidized as a result of this oxidation process.
Next, the silicon nitride side walls
20
are removed by a phosphoric acid etch; see FIG.
1
C. The phosphoric acid etch process is continued until trenches
24
are formed in the substrate
10
; see FIG.
1
D. Typically, the oxidized side walls of the trenches
24
are further implanted with ions to prevent channeling across the trenches.
Subsequently, another poly-Si layer
26
is deposited to fill up the trenches
24
. This second poly-Si layer
26
is back-etched to form the profile shown in FIG.
1
E. The top portion of this poly-Si layer
26
is then oxidized to form silicon oxide
28
as shown in FIG.
1
F. Finally, after pad nitride
14
, pad oxide
12
and the top part of the silicon oxide
28
are removed, the substrate
10
is left with filled trenches
24
, which will function as the isolation regions separating the IC elements to be fabricated on the substrate
10
.
Although the aforesaid conventional process for forming isolation regions has enabled the fabrication of IC elements that do not interfere or cross-talk with one another, the constant miniaturization of VLSI devices dictates that additional improvements be made to the formation of these isolation regions. For example, the aforesaid field oxide formation process is very time-consuming and tends to reduce the throughput of the overall process. More important, as the lithographic line width is reduced to 0.25 &mgr;m or smaller (i.e., sub-quarter-micron or deep sub-micron), it becomes more and more difficult to control the critical dimensions of the isolation regions through conventional exposure and etching schemes. Device miniaturization also reduces the tolerance for misalignment in lithographic and etching processes involved in conventional trench-formation processes. In short, there is plenty of room for improvement in the fabrication of isolation regions of VLSI semiconductor devices.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a new isolation formation process for forming isolation regions between the circuit elements of the VLSI device.
In accordance with the object described above, the present invention provides a method of fabricating oxide trench isolation regions of a VLSI device, which method includes the following processing steps:
Depositing and patterning pad layers on a substrate to form active regions separated from pad-covered regions;
forming side walls at each active region to cover portions of the active region other than its central portion;
depositing a first oxide at the space surrounded by the side walls and the central portion of the active region;
removing the side walls and forming trenches at the active region; forming a second oxide on the substrate to fill the trenches and cover the first oxide, the second oxide and the first oxide together forming an oxide trench isolation region; and
removing the pad layers.
In accordance with the object described above, the present invention provides another method of fabricating isolation regions of a VLSI device, which method includes the following processing steps:
Depositing and patterning pad layers on a substrate to form active regions separated from pad-covered regions;
forming side walls at each active region to cover portions of the active region other than its central portion;
depositing a first oxide at the space surrounded by the side walls and the central portion of the active region;
removing the side walls and forming trenches at the active region;
depositing polysilicon on the substrate to fill the trenches and cover the first oxide,
oxidizing the top portion of the polysilicon to form a second oxide, the second oxide and the first oxide forming an oxide mass, the oxide mass and the bottom portion of the polysilicon together forming a trench isolation region; and
removing the pad layers.
Essentially, the trench isolation fabrication processes disclosed herein have the following significant advantages over those taught in the conventional art:
An advantage of the present invention is that, by eliminating a time-consuming thermal oxidation processing step, the throughput of the VLSI fabrication process is increased.
Another advantage of the present invention is that it is more compatible with deep sub-micron semiconductor processes than the conventional art because the definition of the isolation regions is not dependent upon a single high-resolution lithographic step.
These and other objects, features and advantages of the present invention will no doubt become apparent to those skilled in the art after reading the following detailed description of the preferred embodiment which is illustrated in the several figures of the drawing.
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Blum David S
Bowers Charles
Heller Ehrman White & McAuliffe LLP
Mosel Vitelic Inc.
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