Method for fabricating vertical bipolar junction transistors in

Details Method for fabricating vertical bipolar junction transistors in Method for fabricating vertical bipolar junction transistors in

1994-04-25

1994-11-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 21, 437 62, 437247, 148DIG10, 148DIG12, 148DIG150, H01L 21265

Patent

active

053626591

ABSTRACT:
A method is provided for manufacturing a bipolar transistor, comprising the teps of: 1) abutting a polished surface of a substantially single crystal silicon wafer with a polished surface of an insulating substrate; 2) heating the abutting silicon wafer and insulating substrate at about 200.degree. C. for about 30 minutes to form a bonded wafer having a silicon layer; 3) forming a silicon island from the silicon layer; 4) ion implanting a first dopant species having a first conductivity into the silicon island to form a base region in the silicon island; 5) ion implanting a second dopant species having a second conductivity opposite the first conductivity into the silicon island to form an emitter region and a collector region in the silicon island; 6) ion implanting a third dopant species having the first conductivity into the base region of the silicon island; 7) heating the bonded wafer at a temperature of about 800.degree. C. to activate the first, second, and third dopant species and to repair ion implanting damage to the silicon island; 8) forming electrical contacts to the base, emitter, and collector regions; and 9) forming an oxide layer over the electrical contacts to passivate the electrical contacts.

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Ser. No. 8,074,515 dated Jun. 7, 1993 Imthurn et al. 156/60.

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