Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth from solid or gel state – Using heat
Reexamination Certificate
1993-07-12
2002-10-01
Kunemund, Robert (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Processes of growth from solid or gel state
Using heat
C117S004000, C117S010000, C438S486000, C438S487000, C438S509000
Reexamination Certificate
active
06458200
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating thin-film transistors (referred to hereinafter as TFT) comprising a thin film of a non-single crystal semiconductor, which are highly reliable and suitable for practical applications such as liquid crystal displays and image sensors.
BACKGROUND OF THE INVENTION
Thin-film transistors (TFTs) made with non-single crystal semiconductor produced by chemical vapor deposition (referred to hereinafter as CVD) processes or the like have become of great interest recently.
Since those TFTs are deposited on an insulating substrate by a CVD process or the like, the process can be advantageously carried out in a temperature as low as about 500° C. or even lower. Thus, the process becomes economical, since it allows the use of low-cost soda-lime glass, borosilicate glass, and the like as the substrate.
The TFTs are typically field effect transistors which function in a manner similar to that of the so-called MOSFETs (Metal Oxide Silicon Field-Effect Transistors). As mentioned earlier, the TFTs can be deposited at a low temperature, and moreover, the maximum area thereof is limited only by the dimension of the deposition apparatus. Thus, the TFTs can be freely and easily scaled up with respect to their area, and this is a great advantage. Those TFTs are, therefore, promising as switching devices for active matrix-structured liquid crystal displays consisting of a large number of pixels (picture elements), as well as those for one- or two-dimension image sensors and the like.
The TFTs may be subjected to fine machining (patterning) using the well-established technology of photolithography, and thus they may be integrated in the same manner as, for example, the ICs.
A typical structure of the conventional TFTs is schematically shown in FIG.
2
.
As shown in
FIG. 2
, a typical transistor comprises an insulating glass substrate
20
, a thin film semiconductor
21
consisting of a non-single crystal semiconductor, a source
22
, a drain
23
, a source contact
24
, a drain contact
25
, a gate insulating film
26
, and a gate contact
27
.
In such TFTs, the current between the source [
22
] and the drain [
23
] (the source-to-drain current) can be controlled by applying a voltage to the gate contact [
27
].
The speed of response of the TFT can be given by the following equation:
S=&mgr;·V/L
2
where, L represents the channel length; &mgr;, the carrier mobility; and V, the gate voltage.
The non-single crystal semiconductor layer to be used in the TFTs comprises numerous grain boundaries and the like, and these have greatly reduced the carrier mobility as compared with that of the single crystal semiconductors. The long delay in response ascribed to the low carrier mobility has been a great problem in the non-single crystal semiconductor TFTs. The TFTs using amorphous silicon (referred to hereinafter as a-Si) semiconductors, in particular, were not practically feasible, since the mobility thereof was so low as in the range of about 0.1 to 1 cm
2
·V
−1
·sec
−1
.
In order to overcome such a problem, it is evident from the equation mentioned earlier that there is required to shorten the channel length or to increase the carrier mobility. There have been made, accordingly, many modifications based on such principle.
Shorter channel length, L, is particularly effective for the purpose, since the speed of response increases proportional to the reciprocal of the square of the L.
In the case of fabricating the TFT on a substrate of large area, however, it is obviously difficult with the present photolithographic technology in view of the precision in processing, product yield, production cost, and the like, to reduce the distance between the drain and the source (which corresponds approximately to the channel length) to 10 &mgr;m or less. In short, no effective means to reduce the channel length of the TFT is established yet.
With respect to the measures of increasing the mobility, &mgr;, of the semiconductor layer itself, there have been taken such a measure as incorporating a polycrystalline semiconductor in the active layer of the TFT. This measure requires a relatively high temperature.
It is also to be noted that in TFTs, the electric current at the channel portion is subject to the materials which the source and the drain assemblies are made of. Thus, the source and the drain assemblies are often made polycrystalline, or some treatment is applied thereto to assure good electric contact with the channel portion.
More specifically, a thin film of polycrystalline silicon may be deposited by CVD at the source and the drain areas, but the CVD process requires the process to be carried out at a temperature of 500° C. or higher. As an alternative process, a treatment may be carried out to assure good contact between the channel portion with the source and the drain. The treatment comprises, after forming semiconductor layers as the drain and the source, incorporating thereto an n-type or a p-type impurity by ion-implantation, and then heat-treating the drain and the source at a temperature in the range of from 500 to 800° C.
Both of the processes above require a relatively high temperature to obtain a favorable TFT; no TFTs produced thoroughly in a low temperature process are yet available.
Ion implantation is used for obtaining good electric contacts between the channel potions and the drain and source portions. However, it is extremely difficult to carry out uniform doping of impurities over a large area by ion implantation. This remains as a great hindrance in the future development of large-area liquid-crystal displays and the like.
SUMMARY OF THE INVENTION
The present invention provides, with view to overcome the problems mentioned earlier, a process for fabricating TFTs at a low temperature.
The present invention provides, accordingly, a process for fabricating thin film transistors, which comprises: crystallizing the channel portion by subjecting the channel portion to an excimer laser beam irradiation; and modifying the electric properties of the source and the drain by subjecting the source and the drain to excimer laser irradiation in a step independent to the first step of crystallizing the channel portion.
The two-step laser annealing process for TFTs according to the present invention is carried out at a low temperature.
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Laser Annealing of Semiconductors, J.M. Poate-Editor, Academic Press, Inc., 1982, Chapter 13-“Factors Influencing Applications”, pp. 479-489.
T. Sameshima et al., “XeCI Excimer Laser Annealing Used to Fabricate Poly-Si TFT's,” Japanese Journal of Applied Physics, vol. 28, No. 10, Oct. 1989, pp. 1789-1793.*
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S. Wolf, et alSilicon P
Kunemund Robert
Nixon & Peabody LLP
Robinson Eric J.
Semiconductor Energy Laboratory Co,. Ltd.
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