Method for fabricating storage electrode of dynamic random acces

Details Method for fabricating storage electrode of dynamic random acces Method for fabricating storage electrode of dynamic random acces

1993-11-12

1995-12-19

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 60, 437233, 437919, H01L 218242

Patent

active

054768055

ABSTRACT:
A method for fabricating a storage electrode of a DRAM cell capable of preventing impurities from excessively moving from the storage electrode to diffusion regions. The storage electrode is formed by a double formation of polysilicon layers. An undoped polysilicon layer 11 is primarily deposited over the entire exposed surface of the resulting structure to a thickness corresponding to 40 to 50% of a predetermined thickness of the storage electrode. A doped polysilicon layer is secondarily deposited over the undoped polysilicon layer to a thickness corresponding to 60 to 50% of the predetermined thickness of the storage electrode. The doped polysilicon layer and the undoped polysilicon layer are subjected to a patterning so that predetermined portions thereof are removed so as to form the storage electrode.

REFERENCES:
patent: 4363828 (1982-12-01), Brodsky et al.
patent: 5071783 (1991-12-01), Taguchi et al.
patent: 5286668 (1994-02-01), Chou
Wolf, "Silicon Processing for the VLSI Era" vol. 1; 1989, Lattice Prss, pp. 177-182.

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