Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-07-21
2001-08-21
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C216S018000, C216S038000, C438S734000, C438S737000
Reexamination Certificate
active
06277761
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for fabricating stacked vias or electrical plated-through holes stacked one above the other for microelectronic components. A known configuration is disclosed in U.S. Pat. No. 5,710,462.
U.S. Pat. No. 5,328,553 describes a method for filling the contact holes.
Nowadays it is generally customary to provide a plurality of wiring planes in microelectronic components, the planes each being isolated from one another by intervening insulating layers. In order to connect together two wiring planes lying one above the other or to establish a contact between the first wiring plane and the microelectronic structures lying underneath, before the top wiring plane is applied, a through hole is formed in the intervening insulating layer and is filled with a conductive material. The top wiring plane is then applied and patterned.
If two wiring planes which do not lie directly one above the other are to be connected to one another, or if the microelectronic structures lying below the first wiring plane are to be connected directly to the second wiring plane, i.e. at least one further wiring plane lies in between, a stacked via is usually provided, as is explained in more detail below.
What has turned out to be disadvantageous in the case of the prior art is the fact that the metal area of a metal landing pad has to be made large enough that a lower via is definitely covered by it, or an upper via definitely lands on it.
Since this configuration is associated with a large space requirement, attempts are made to use smaller metal landing pads, thereby giving rise to the risk of the upper via reaching the side edge of the pad and the subsequently sputtered liner not being tight on account of pitting in the metal or dielectric. In particular, such small metal areas are difficult to reach in terms of resist engineering, which necessitates complicated and costly resist techniques or entails the risk of increased defect densities due to resist plugs tilting over.
Although the problem of the vias meeting the metal side edges with a non-tight liner can be supplemented by making the metal landing pads appropriately large, this entails a high space requirement. Liner deposition by sputtering can also be replaced by more expensive chemical vapor deposition (CVD).
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating stacked vias that overcomes the above-mentioned disadvantages of the prior art methods of this general type, which enables space to be saved without increased process risks.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating stacked vias for microelectronic components. A first patterned interconnect layer is provided on a substrate. A first insulating layer is applied on the first patterned interconnect layer. A first via is formed in the first insulating layer and is in contact with the first patterned interconnect layer, the forming of the first via step includes the steps of: forming a first hole in the first insulating layer by an anisotropic etching process; applying a first liner to the first hole; and filling the first hole with an electrically conductive material. A second patterned interconnect layer is then applied on the first insulating layer, leaving free a region around the first via. A second insulating layer is applied on the second patterned interconnect layer and on the region left free around the first via. A second via is formed in the second insulating layer such that the second via meets the first via directly, the forming of the second via step includes the steps of: forming a second hole in the second insulating layer by the anisotropic etching process; applying a second liner to the second hole; and filling of the second hole with the electrically conductive material. A further second via is formed in the second insulating layer and is in contact with the second patterned interconnect layer, and a formation of the further second via takes place simultaneously with a formation of the second via. The forming of the further second via step includes the steps of: forming a further second hole in the second insulating layer by the anisotropic etching process and by overetching the further second hole where the second patterned interconnect layer serves as a vertical etching stop during the overetching of the further second hole to allow the simultaneous formation of the second via and the further second via; applying a further second liner to the further second hole; and filling of the further second hole with the electrically conductive material.
Compared with the known solution approach, the method according to the invention has the advantage that a critical structure size is obviated during the lithography, namely that of the metal landing pad. Furthermore, a considerable amount of space is saved and the process risks occurring with regard to the metal landing pads are avoided. It is necessary to ensure merely that the insulating layer relating to the upper via is etched through.
The idea on which the present invention is based consists generally in forming the second patterned interconnect layer on the first insulating layer, leaving free a region around the first via, and not on the first via. The second insulating layer is then formed on the second interconnect layer and the region left free around the first via. Finally, the second via is formed in the second insulating layer in such a way that it meets the first via directly. In this respect, it shall be noted that the first interconnect layer may also be a microelectronic structure and need not necessarily be a metallic wiring plane.
According to the invention, the formation of the further second via takes place at the same time as the formation of the second via. Thus, the through-plating from the second to the third interconnect layer does not require an additional process step.
According to the invention, the second patterned interconnect layer is configured in such a way that, during the overetching, it forms a vertical etching stop for the further second via. As a result, the overetching can progress only in the horizontal direction, which has a less disturbing effect due to the anisotropic nature of the etching process.
According to the invention, a third patterned interconnect layer is provided on the second insulating layer and is in contact with the second via. A stack of two vias is thus produced.
In accordance with an added feature of the invention, the first liner, the second liner and the further second liner are formed from titanium or titanium nitride. Whereas the electrically conductive material contains tungsten.
In accordance with another feature of the invention, the anisotropic etching process is a plasma etching process.
In accordance with an additional feature the invention, the first liner, the second liner and the further second liner are sputtered on.
In accordance with a preferred development, the following steps are additionally carried out: applying a third patterned interconnect layer on the second insulating layer, leaving free a region around the second via and applying a third insulating layer on the third interconnect layer and the region left free around the second via. A third via in the third insulating layer is formed such that it meets the second via directly. Thus, even three or even more vias can be stacked one above the other.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating stacked vias, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, t
Diewald Wolfgang
Weber Detlef
Greenberg Laurence A.
Lerner Herbert L.
Powell William
Siemens Aktiengesellschaft
Stemer Werner H.
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