Method for fabricating stacked capacitors of semiconductor devic

Details Method for fabricating stacked capacitors of semiconductor devic Method for fabricating stacked capacitors of semiconductor devic

1995-12-26

1997-08-19

Tsai, Jey

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

H01L 2170, H01L 2700

Patent

active

056588178

ABSTRACT:
A method for fabricating capacitors of a semiconductor device capable of forming a capacitor structure providing a higher capacitance than the conventional pin-shaped structure. The method includes forming a lower insulating layer over a semiconductor substrate, forming a contact hole in the lower insulating layer, forming a first conduction layer over the resulting structure, etching the first conduction layer and the lower insulating layer at a desired region to a desired depth of the lower insulating layer, thereby forming a groove, sequentially forming a second conduction layer and a sacrificial film over the resulting structure, anisotropically etching the sacrificial film by use of said contact mask at a region where it fills the contact hole, forming a third conduction layer over the resulting structure, anisotropically etching the third conduction layer, the sacrificial film and the second conduction layer at a region where they fill the groove, forming, on side walls of the groove, spacers comprised of the portions of the second conduction layer left on the side walls of the groove, respectively, and removing the sacrificial film, thereby forming storage electrodes having an increased surface area.

REFERENCES:
patent: 5236859 (1993-08-01), Bae
patent: 5248628 (1993-09-01), Okabe et al.
patent: 5284787 (1994-02-01), Ahn

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