Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
1998-01-27
2001-02-06
Tsai, Jey (Department: 2012)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S254000
Reexamination Certificate
active
06184152
ABSTRACT:
The present invention relates generally to a dynamic random access memory (DRAM), and particularly to a self-aligned stacked capacitor for an array of memory cells for a DRAM.
BACKGROUND OF THE INVENTION
A DRAM is a semiconductor device for storing digital information. Data, as digital information, can be written to and read from a DRAM. DRAMS are fabricated using integrated circuit technology.
A DRAM is made of many storage nodes or memory cells and each memory cell has a memory cell transistor and a capacitor. The capacitor is an important element of the memory cell because it stores the digital information. Trench capacitors and stack capacitors are the two major types of DRAM cell capacitors.
The higher the capacitance of the capacitor the better. Higher capacitance improves the data sensing margin and increases the shrinkability of the memory cell. One way to increase capacitance is to increase the surface area of the capacitor (capacitor area). The trench capacitor increases the capacitor area by digging a deep trench inside the bulk silicon. The stack capacitor increases the capacitor area by raising the height of the capacitor above the surface of the silicon wafer. One particular type of stack capacitor has a cylindrical shape to increase the capacitor area without increasing the area and height of the memory cell. Stack capacitors are also referred to as capacitor-over-bit-line (COB) capacitors.
DRAM density is ever-increasing and the size of memory cell area on the DRAM chip is decreasing. Each memory cell capacitor uses a large amount of space on the DRAM. The need for memory cell capacitors to be isolated from each other also uses space. To increase DRAM density, a method is needed to further increase the size of the DRAM memory cell capacitor and to decrease the spacing between memory cell capacitors.
SUMMARY OF THE INVENTION
A method is provided for fabricating an array of memory cells for a dynamic random access memory. Each memory cell has an associated capacitor. An array of memory cell transistors is formed and each memory cell transistor has a source, drain and gate. The drain is coupled to a bit line, and the gate is coupled to a word line. A lower conductive layer is formed over the array of memory cell transistors. The lower conductive layer is electrically coupled to the source of the memory cell transistors. An temporary insulation layer is formed over the lower conductive layer. A portion of the temporary insulation layer and the lower conductive layer are removed to form an electrically separate capacitor bottom plate for each memory cell and an inter-capacitor isolation region. A lateral portion of the temporary insulation layer is removed to form a capacitor sidewall spacing region. A protective layer is formed to fill the inter-capacitor isolation region and the capacitor sidewall spacing region. The temporary insulation layer is removed to expose a portion of the lower conductive layer. A portion of the exposed portion of the lower conductive layer is removed to form a U-shaped capacitor bottom plate. The protective layer is removed and a capacitor dielectric is formed. An upper conductive layer is formed to function as a top plate of the capacitor.
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Integrated Silicon Solution Inc.
Pennie & Edmonds LLP
Tsai Jey
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