Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-05-24
2001-05-22
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S113000, C438S125000
Reexamination Certificate
active
06235554
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and specifically to the packaging of semiconductor dice.
BACKGROUND OF THE INVENTION
Semiconductor dice or chips are typically individually packaged for use in plastic or ceramic packages. This is sometimes referred to as the first level of packaging. The package is required to support, protect, and dissipate heat from the die and to provide a lead system for power and signal distribution to the die. The package is also useful for performing burn-in and functionality testing of the die.
One type of semiconductor package is referred to as a “chip scale package”. Chip scale packages are also referred to as “chip size packages”, and the dice are referred to as being “minimally packaged”. Chip scale packages can be fabricated in “uncased” or “cased” configurations. Uncased chip scale packages have a “footprint” (peripheral outline) that is about the same as an unpackaged die. Cased chip scale packages have a peripheral outline that is slightly larger that an unpackaged die. For example, a footprint for a typical cased chip scale package can be about 1.2 times the size of the die contained within the package.
Typically, a chip scale package includes a substrate bonded to the face of the die. The substrate includes the external contacts for making outside electrical connections to the chip scale package. The substrate for a chip scale package can comprise a flexible material, such as a polymer tape, or a rigid material, such as silicon, ceramic, glass or FR-4. The external contacts for one type of chip scale package include solder balls arranged in a dense array, such as a ball grid array (BGA), or a fine ball grid array (FBGA). These dense arrays permit a high input/output capability for the chip scale package. For example, a FBGA on a chip scale package can include several hundred solder balls.
One aspect of chip scale packages is that the substrates and external contacts are difficult to fabricate. In addition, reliable electrical connections must be made to die contacts (e.g., bond pads) on the die contained within the package. Further, electrical paths must be formed on the substrate between the die contacts and the external contacts. With increasing contact densities, forming these electrical paths becomes increasingly expensive, and requires more complex fabrication processes. Accordingly, improved fabrication processes for chip scale packages are needed.
Another aspect of chip scale packages is the mounting of the packages to supporting substrates, such as printed circuit boards, and ceramic modules. This is sometimes referred to as the second level of packaging. Typically, the packages are surface mounted by reflowing the external contacts on the package to corresponding contacts on the supporting substrate. It would be advantageous for chip scale packages to be capable of denser second level packaging arrangements than conventional surface mount arrangements.
In view of the foregoing, the present invention is directed to an improved chip scale package and method of fabrication.
SUMMARY OF THE INVENTION
In accordance with the present invention an improved stackable chip scale package, and a method for fabricating the package, are provided. Also provided are improved electronic assemblies constructed using multiple packages in a stacked configuration.
The package, simply stated, comprises: a substrate, a die mounted to the substrate, a first set of external contacts on a first surface of the substrate, and a second set of external contacts on a second opposing surface of the substrate. The substrate includes a die mounting site, such as a cavity sized and shaped to retain the die. In addition, an interconnect opening and a wire bonding cavity in the substrate permit electrical connections (e.g., wire bonds, TAB bonds) to be made between the die, and conductors on the substrate.
The package also includes conductive vias formed in the substrate using a laser machining and etching process. The conductive vias electrically connect the first set of external contacts to the second set of external contacts. In addition, the first and second sets of external contacts have a mating configuration that permits multiple packages to be stacked, and electrically interconnected to one another and to a supporting substrate (e.g., PCB, module substrate).
In an illustrative embodiment the package substrate comprises silicon, but alternately can be germanium, ceramic or other etchable material. Fabrication of the package can be performed at the wafer level, by providing a silicon wafer on which multiple packages are formed, and then singulated into individual packages. Stacking of the packages can also be performed at the wafer level, in which case singulation can be on stacked wafers containing multiple packages.
An exemplary fabrication sequence can include the initial step of laser machining vias through the substrate. The die mounting cavities and interconnect cavities can then be formed in the substrate using one or more etch masks, and a wet etchant, such as KOH or TMAH. During the etch step, or during a separate etch step, the laser machined vias can also be etched. Etching the laser machined vias cleans and enlarges the vias.
Following etching, sidewalls of the vias can be insulated, and the vias filled with a conductive material, such as a deposited metal, or a conductive polymer. The conductive material can completely fill the vias, or can comprise thin layers that cover only the sidewalls of the vias. Depending on the conductive material, exemplary deposition processes include sputtering, CVD, electroless deposition, and filling the vias by capillary action. Subsequent to, or during, filling of the vias, patterns of conductors can be formed on the substrate, in electrical communication with the conductive material contained in the vias.
Following formation of the conductors, the external contacts can be formed on the substrate in electrical communication with the conductors. In the illustrative embodiment, the first set of external contacts comprise bumped members, such as solder balls, and the second set of external contacts comprise flat pads adapted for mating engagement with the bumped members. Alternately, other mating structures such as bumps and recesses, or pins and openings, can be employed to permit mating engagement of a first set of contacts on a package, to a second set of contacts on an adjacent stacked package.
Following formation of the external contacts, the dice can be mounted to the substrates, and electrically connected to the conductors and conductive vias. Exemplary processes for forming the electrical connections include wire bonding, TAB bonding and reflow solder bonding. The packages on the wafer can then be singulated into separate packages by cutting or shearing the wafer. Stacking and bonding of the contacts on adjacent stacked packages can be with a solder reflow process, or with a deposited and cured conductive polymer.
If the dice have been provided as known good die (KGD), the packages need not require further testing. Alternately, full functionality and burn-in tests can be performed on the packages, or on the stacked assemblies.
REFERENCES:
patent: 3648131 (1972-03-01), Stuby
patent: 4505799 (1985-03-01), Baxter
patent: 4649418 (1987-03-01), Uden
patent: 4725924 (1988-02-01), Juan
patent: 4731645 (1988-03-01), Parmentier et al.
patent: 4829666 (1989-05-01), Haghiri-Tehrani
patent: 4931853 (1990-06-01), Ohuchi et al.
patent: 4996587 (1991-02-01), Hinrichsmeyer et al.
patent: 5022580 (1991-06-01), Pedder
patent: 5043794 (1991-08-01), Tai et al.
patent: 5048179 (1991-09-01), Shindo et al.
patent: 5063177 (1991-11-01), Geller et al.
patent: 5107328 (1992-04-01), Kinsman et al.
patent: 5138434 (1992-08-01), Wood et al.
patent: 5155067 (1992-10-01), Wood et al.
patent: 5191511 (1993-03-01), Sawaya
patent: 5239198 (1993-08-01), Lin et al.
patent: 5384689 (1995-01-01), Shen
patent: 5397917 (1995-03-01), Ommen et al.
patent: 5422514 (1995-06-01), Griswold et al.
patent: 5
Akram Salman
Farnworth Warren M.
Wood Alan G.
Gratton Stephen A.
Micro)n Technology, Inc.
Picardat Kevin M.
LandOfFree
Method for fabricating stackable chip scale semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating stackable chip scale semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating stackable chip scale semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2554455