Method for fabricating silicon-on-insulator structures

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 65, 437 67, 437 72, 437 78, 437927, 437974, 437 21, 437203, 148 332, 148 335, 148DIG135, 357 49, 357 55, H01L 2176

Patent

active

050574507

ABSTRACT:
A fabrication method for forming SOI structures where perfect material is grown epitaxially on a substrate and then, through a series of selective etches and oxidations, an insulating layer is formed below the epitaxial silicon. In the method, low temperature epitaxial techniques are employed to grow a layered structure including a first layer p++ silicon on a substrate wafer, a layer of intrinsic silicon is then formed on the first p++ silicon layer, and a second layer of p++ silicon is formed on the intrinsic silicon layer, and a finally a layer of p-silicon is fabricated on top of the second p++ silicon layer. Grooves are formed through the p-layer, the second p++ silicon layer, the intrinsic silicon layer, and stopped in the first p++ silicon layer. An etch is then employed to remove the intrinsic layer long enough for the p++ silicon layer to be totally undercut, leaving an air gap between the two p++ silicon layers. An oxidation step is then performed to form a bottom insulator consisting of the oxidized first p++ silicon layer and on an upper insulator consisting of the oxidized second p++ silicon layer.

REFERENCES:
patent: 3345222 (1967-10-01), Nomura et al.
patent: 3607480 (1971-09-01), Harrap et al.
patent: 3731375 (1973-05-01), Agusta et al.
patent: 4125427 (1978-11-01), Chen et al.
patent: 4760036 (1988-07-01), Schubert
patent: 4786609 (1988-11-01), Chen
patent: 4829018 (1989-05-01), Wahlstrom
patent: 4888300 (1989-12-01), Burton
patent: 4925805 (1990-05-01), van Ommen et al.
patent: 4929571 (1990-05-01), Omura et al.
patent: 4982263 (1991-01-01), Spratt et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for fabricating silicon-on-insulator structures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating silicon-on-insulator structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating silicon-on-insulator structures will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-990742

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.