Method for fabricating silicon-on-insulator device wafer

Details Method for fabricating silicon-on-insulator device wafer Method for fabricating silicon-on-insulator device wafer

1996-10-03

1998-09-22

Valentine, Donald R.

Electrolysis: processes, compositions used therein, and methods

Electrolytic erosion of a workpiece for shape or surface...

Eroding workpiece of nonuniform internal electrical...

205660, 205662, 205674, C25F 312

Patent

active

058109943

ABSTRACT:
A silicon on-insulator device wafer having a very thin monocrystalline film with uniform thickness. It is fabricated by vias technique in which a monocrystalline silicon film on an insulator is etched with a base silicon etching solution in an etch apparatus by applying a vias in such a way that the solution may serve as an anode and the substrate of SOI structure as a cathode. The presence of the insulator generates vacancies in a lower region of the monocrystalline silicon film and electrons in the substrate, so that the lower region charged with the vacancies is not removed by the base silicon etching solution, thereby leaving a highly uniform, thin monocrystalline silicon film.

REFERENCES:
patent: 4303482 (1981-12-01), Buhne et al.
patent: 5066610 (1991-11-01), Chen et al.
patent: 5233218 (1993-08-01), Miura
patent: 5286671 (1994-02-01), Kurtz et al.
patent: 5458735 (1995-10-01), Richter et al.
patent: 5529950 (1996-06-01), Hoenlein et al.

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