Fishing – trapping – and vermin destroying
Patent
1995-06-15
1996-08-27
Quach, T. N.
Fishing, trapping, and vermin destroying
437 24, 437193, 437200, 437956, H01L 21265, H01L 21283
Patent
active
055500790
ABSTRACT:
A method for fabricating a silicide shunt for use in dual-gate CMOS devices makes use of a nitrogen-containing silicide layer overlying the juncture between the P-type polysilicon layer and the N-type polysilicon layer. The nitrogen-containing silicide layer is formed by implanting nitrogen-containing ions, such as .sup.28 N.sub.2.sup.+, into a partial or overall silicide shunt which was originally deposited over the P-type polysilicon layer and N-type polysilicon layer. Therefore, the nitrogen-containing silicide layer can serve as a diffusion barrier layer retarding the lateral dopant diffusion of these polysilicon layers via the silicide shunt.
REFERENCES:
patent: 4703552 (1987-11-01), Baldi et al.
patent: 5103272 (1992-04-01), Nishiyama
patent: 5190893 (1993-03-01), Jones, Jr. et al.
patent: 5355010 (1994-10-01), Fujii et al.
patent: 5369304 (1994-11-01), Lesk et al.
patent: 5389575 (1995-02-01), Chin et al.
patent: 5468669 (1995-11-01), Lee et al.
patent: 5508212 (1996-04-01), Wang et al.
"Three Dual Polysilicon Gate CMOS . . .", IBM Technical Disclosure Bulletin, vol. 27, No. 11. Apr. 1985, pp. 6652-6655.
Quach T. N.
Top Team/Microelectronics Corp.
LandOfFree
Method for fabricating silicide shunt of dual-gate CMOS device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating silicide shunt of dual-gate CMOS device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating silicide shunt of dual-gate CMOS device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1056036