Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-05-03
2001-10-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S785000
Reexamination Certificate
active
06306722
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a shallow trench isolation (STI) structure. More particularly, the present invention relates to a method for fabricating a shallow trench isolation structure filled with doped silicon dioxide.
2. Description of the Related Art
In an integrated circuit, an isolation structure is needed to isolate devices. Since a shallow trench isolation structure has advantages of scalability and a good isolation ability, this technology is preferably used in the sub-micron process.
In the conventional method for forming a shallow trench isolation structure, an anisotropic etching process is performed with silicon nitride serving as a mask to form a steep trench in a substrate. An undoped silicon dioxide layer is formed within the trench and a shallow trench isolation structure is thus formed. The substrate is then dipped in a dilute hydrofluoric acid (HF) solution to remove impurities formed during the above processes.
Usually, a portion of the undoped silicon dioxide layer is lost during the subsequent dipping process so that defects are formed in the undoped silicon dioxide layer mid the reliability of the shallow trench isolation structure is decreased. An annealing, process is performed at about 1100° C. to densify the undoped silicon dioxide layer before the dipping process to prevent the undoped silicon dioxide layer from losing material.
However, due to a large difference in thermal expansion coefficients and Young's modulus between the substrate and the undoped silicon dioxide layer, significant substrate stress of several hundred MPa occurs during the annealing process. Due to this stress, crystallographic detects occur in the undoped silicon dioxide layer, which defects enhance junction leakage and sub-threshold leakage. In dense pattern areas and high packing density memory devices, this causes the devices to fail.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method for fabricating a shallow trench isolation structure that reduces stress incurred during the annealing process, junction leakage and sub-threshold leakage.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for fabricating a shallow trench isolation structure. The method includes the following steps. A pad oxide layer and a silicon nitride layer are formed in sequence on a substrate. A trench formed in the substrate, and a liner oxide layer is formed on a sidewall of the trench. A doped silicon dioxide layer is formed on the silicon nitride layer and fills the trench. An annealing process is performed to densify the doped silicon dioxide layer. A portion of the doped silicon dioxide layer is removed to expose the silicon nitride layer by a planarization process.
In the invention, the doped silicon dioxide layer doped with germanium, nitrogen or refractory metals is used to form the shallow trench isolation structure. The thermal expansion coefficient and Young's modulus of the doped silicon dioxide layer is influenced by the dopants. Therefore, the thermal expansion coefficient and Young's modulus of the doped silicon dioxide layer are modulated by controlling the doping level to be comparable with the substrate. As a result stress incurred during the annealing process, is reduced. Furthermore, junction leakage and sub-threshold leakage are both reduced and the annealing process can be performed at lower temperature. Additionally, since the hydrofluoric acid etching rate of the doped silicon dioxide layer is different from that of the silicon dioxide layer, the kink effect can be also eliminated.
It is to be that both the foregoing general description, and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Wolf, “Silicon Processing for the VLSI Era”, vol. 1 pp. 189-191, 1986.
Chen Coming
Lur Water
Yang Gwo-Shii
Yew Tri-Rung
Niebling John F.
Pompey Ron
United Microelectronics Corp.
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