Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-09-07
2004-08-10
Thompson, Craig A. (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06774008
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating shallow trench isolation (STI) between deep trench capacitors and, more particularly, a logic-process compatible method for fabricating shallow trench isolation (STI) between deep trench capacitors of trench-capacitor dynamic random access memory (DRAM) devices.
2. Description of the Prior Art
Trench-capacitor DRAMdevices are known in the art. Typically, a trench-storage capacitor consists of a very-high-aspect-ratio contact-style hole pattern etched into the substrate, a thin storage-node dielectric insulator, a doped low-pressure chemical vapor deposition (LPCVD) polysilicon fill, and buried-plate diffusion in the substrate. The doped LPCVD silicon fill and the buried plate serve as the electrodes of the capacitor. A dielectric isolation collar in the upper region of the trench prevents leakage of the signal charge from the storage-node diffusion to the buried-plate diffusion of the capacitor. After forming the trench capacitors, shallow trench isolation (STI) regions are formed on the substrate between the trench capacitors.
Generally, the prior art STI process for trench capacitor DRAM devices includes the following main steps:
1. Deep trench (DT) process;
2. Cap hard mask layer deposition and patterning;
3. Hard mask etching and photoresist strip;
4. STI trench etching and hard mask strip; and
5. STI gap fill and planarization.
Referring to
FIG. 1
to
FIG. 5
of schematic cross-sectional views showing the fabrication of STI regions between trench capacitors according to the prior art method. As shown in
FIG. 1
, a semiconductor chip
1
comprising a logic area
11
and a memory array area
12
is provided. As indicated, a plurality of trench capacitors
20
have been formed in the semiconductor substrate
10
within the memory array area
12
of the semiconductor chip
1
. Typically, each of the trench capacitors
20
comprises a buried plate diffusion (not shown) acting as one electrode of the capacitor, a poly storage node
24
serving as the other electrode of the capacitor, and a node dielectric
22
between the two electrodes. A collar oxide layer
26
is formed on an upper portion of the deep trenches. A pad nitride layer
14
laid over the semiconductor substrate
10
is typically used to define the openings of the deep trenches. At this stage, after forming the trench capacitor structures
20
, there is a recess
28
left on each top of the trench capacitor structures
20
.
As shown in
FIG. 2
, a doped silicate glass layer
32
is deposited on the surface of the semiconductor chip
1
. The doped silicate glass layer
32
has a thickness of about 3000 to 4000 angstroms. Typically, the doped silicate glass layer
32
is made of borosilicate glass (BSG) or borophosposilicate glass (BPSG). The doped silicate glass layer
32
covers the pad nitride
14
and fills the recesses
28
.
As shown in
FIG. 3
, a bottom anti-reflection coating (BARC)
34
is deposited on the doped silicate glass layer
32
, followed by photoresist coating. A conventional lithographic process and subsequent baking process are then carried out to pattern the photoresist coating, thereby forming a photo mask
36
defining memory array area trench openings
43
and logic area trench openings
45
therein.
As shown in
FIG. 4
, using the photo mask
36
as an etching mask, a plasma dry etching is performed to etch the BARC
34
, the doped silicate glass layer
32
, the pad nitride
14
, the silicon substrate
10
, a portion of the storage node
24
, and a portion of the collar oxide
26
through the memory array area trench openings
43
within the memory array area
12
, thereby forming isolation trenches
53
, and to etch the BARC
34
, the doped silicate glass layer
32
, the pad nitride
14
, the silicon substrate
10
through the logic area trench openings
45
within the logic area
11
, thereby forming isolation trenches
55
. Thereafter, the remaining photo mask
36
, the BARC
34
, and the doped silicate glass layer
32
are removed. Finally, as shown in
FIG. 5
, the isolation trenches
53
and
55
are filled with gap fill dielectric
58
and planarized.
However, there are several problems with the above-described prior art STI method for trench capacitor DRAM devices. First, the thick hard mask (doped silicate glass layer
32
) leads to bad critical dimension (CD) uniformity and large iso/dense CD bias. Secondly, the STI trench recipe is difficult to develop because of the complex structure of the trench capacitor. Thirdly, the above-described prior art STI method for trench capacitor DRAM devices is not compatible with the logic processes.
SUMMARY OF INVENTION
Accordingly, the primary object of the present invention is to provide an improved STI method for trench capacitor DRAM devices to form STI between trench capacitors and such method is compatible with the logic processes.
According to one preferred embodiment of this invention, a method for fabricating shallow trench isolation (STI) between deep trench capacitors is disclosed. A semiconductor substrate having thereon a patterned pad layer is provided. The semiconductor substrate has a plurality of deep trench capacitors formed therein, each of which comprising a buried plate in the semiconductor substrate serving as one electrode of the deep trench capacitor, a storage node serving as the other electrode of the deep trench capacitor, a node dielectric layer between the buried plate and the storage node, and a collar oxide disposed at an upper portion of the deep trench capacitor. A dielectric layer is filled into a capacitor top recess on each of the deep trench capacitors. The studded dielectric layer has a top surface that is coplanar with the pad layer. A buffer layer is deposited over the semiconductor substrate. A photo mask defining trench openings is formed over the buffer layer. A plasma etching process is performed to etch the buffer layer, the pad layer, and then etching into the semiconductor substrate selective to the dielectric layer and the collar oxide that both keep the deep trench capacitors intact through the trench openings, thereby forming isolation trenches between the deep trench capacitors. After stripping the photo mask, the isolation trenches are filled with gap filling material.
Other objects, advantages, and novel features of the claimed invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6140206 (2000-10-01), Li et al.
Su Yi-Nan
Sun Nathan
Hsu Winston
Thompson Craig A.
United Microeletronics Corp
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