Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-01-25
2003-04-01
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S434000, C438S435000
Reexamination Certificate
active
06541350
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for manufacturing semiconductor devices, and more particularly, to a method for fabricating shallow trench isolation in semiconductor devices.
BACKGROUND OF THE INVENTION
With the fast developments of semiconductor process technology, the dimensions of integrated circuits (ICs) are rapidly scaled down into sub-micron level. Oxide isolation regions are usually incorporated with active areas of IC devices during the period of semiconductor processes. In general, a local oxidation (LOCOS) process is employed to form these oxide isolation regions, but the LOCOS process may induce a bird's beak structure such that the active areas of devices are unacceptably encroached. Therefore, shallow trench isolation (STI) process is widely used to form isolation regions between active areas. The conventional process of fabricating shallow trench isolation is shown in
FIG. 1A
to FIG.
1
D.
Referring to
FIG. 1A
, a pad oxide layer
102
and a silicon nitride layer
104
are sequentially formed on a substrate
100
, and then a shallow trench
106
is formed thereon by a photolithography and etching process. Afterward, a thermal oxidation process is carried out to form a lining oxide layer
110
on sidewall
108
of shallow trench
106
.
Referring to FIG.
1
B and
FIG. 1C
, an implant process is performed to form a siliconoxynitride (SiON) layer
112
on the lining oxide layer
110
. Afterwards, a high-density plasma chemical vapor deposition (HDPCVD) process is carried out to deposit a silicon oxide layer
120
on the silicon nitride layer
104
and inside the trench. The excess silicon oxide over the silicon nitride layer
104
is removed away by a chemical mechanical polishing (CMP) process.
Generally, a thicker lining oxide layer
110
is necessary to be deposited in conventional process. Thereafter, a siliconoxynitride (SiON) layer
112
is formed by a nitrogen-implanted process (
114
,
116
,
118
).
However, the thicker lining oxide layer
110
, on one hand, will consume a large amount of substrate
100
material such that the trench
106
easily encroach outwardly on the active areas (not shown) resulting in worse trench topography. On the other hand, if the lining oxide layer
110
is thinner, the crystalline structure of trench sidewall
108
may be damaged by a large number of ions induced by high-density plasma at the start-up period of the process. Furthermore, the isolation effect of the shallow trench
106
will be severely downgraded after the silicon oxide plug is entirely generated.
In addition, the implant angles for operating ion implanter must be switched frequently to adapt to various processes so that the manufacturing time and cost of trench will considerably increase.
Referring to
FIG. 1D
, the silicon nitride layer
104
is stripped by hot phosphoric acid (H
3
PO
4
) and the pad oxide layer
102
is etched away by hydrofluoric acid (HF). At the time, a silicon oxide plug
122
is left inside the shallow trench
106
. While the pad oxide layer
102
is being removed, the silicon oxide plug
122
and the lining oxide layer
110
are also simultaneously etched.
Generally speaking, the etch rate of the pad oxide layer
102
formed by thermal oxidation is smaller than that of the silicon oxide plug
122
formed by HDPCVD process when using HF as an etchant. Consequently, after the lining oxide layer
110
is removed, the corroded edge of silicon oxide plug
122
may result in current leakage. The thicker siliconoxynitride layer
112
is deposited, the more severe the silicon oxide plug
122
is damaged. Since a long time of etching process is implemented, thus the silicon oxide plug
122
is strictly encroached, making the edge recess of the silicon oxide plug
122
acutely, which evokes many problems, such as sub-threshold voltage and current leakage.
SUMMARY OF THE INVENTION
In view of the problems encountered with the foregoing conventional shallow trench isolation, for example, there are some degree of substrate overuse, plasma damage of crystalline structure of trench, and edge recess of the silicon oxide plug.
As a result, the primary object of the present invention is, before the HDPCVD process is implemented, that the trench is implanted by nitrogen ions to form silicon nitride, followed that the siliconoxynitride layer is formed by thermal oxidation process. During the thermal oxidation process, the siliconoxynitride layer can be formed with ease by a small amount of substrate, correspondingly increasing the regions of the active area.
Another object is using the siliconoxynitride layer to prevent the crystalline structure of the trench from high-density plasma damages.
Still another object is utilizing the siliconoxynitride so as to prohibit the silicon oxide plug form recess.
In the preferred embodiment of the present invention, a pad oxide layer and a mask layer is sequentially formed on a substrate. Afterwards, an opening is formed through the mask layer and the pad oxide layer such that regions of the substrate are exposed. Thereafter, the exposed regions are etched to form trenches inside the substrate. Next, nitrogen ions are implanted into the sidewall of the trenches to form a silicon nitride layer, and then a siliconoxynitride layer is formed inside the sidewall of the trenches. Subsequently, a silicon oxide layer is formed on the siliconoxynitride layer and on the mask layer. The excess portion of the silicon oxide layer over said mask layer is removed to expose the mask layer, and then the mask layer is removed away. Finally, the pad oxide layer is removed by using hydrofluoric acid (HF).
In summary, the silicon nitride layer is formed prior to the formation of the silicon oxide. Thereafter, the siliconoxynitride layer is formed by the thermal oxidation process, which can effectively prevent the crystalline structure of trench from high-density plasma damage to reduce the probability of current leakage. At the same time, the siliconoxynitride layer is utilized for protecting the silicon oxide plug.
REFERENCES:
patent: 6156620 (2000-12-01), Puchner et al.
patent: 6238998 (2001-05-01), Leobandung
patent: 6323106 (2001-11-01), Huang et al.
Stanley Wolf Ph.D. and Richard N. Tauber Ph.D. in Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, 1986, pp. 209-210, 531-534.
Brewster William M.
Macronix International Co. Ltd.
LandOfFree
Method for fabricating shallow trench isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating shallow trench isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating shallow trench isolation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3054065