Method for fabricating semiconductor wafer with enhanced...

Details Method for fabricating semiconductor wafer with enhanced... Method for fabricating semiconductor wafer with enhanced...

2006-12-20

2009-11-03

Smoot, Stephen W (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S975000, C257SE23179

Reexamination Certificate

active

07611961

ABSTRACT:
A manufacturing method of a semiconductor wafer includes forming a plurality of alignment trenches in the wafer substrate. A dielectric layer is formed over the substrate filling the trenches. A planarization process is performed to remove the dielectric layer above the substrate. A photolithograph process is subsequently performed to selectively remove the dielectric layer formed in the trenches in the alignment area.

REFERENCES:
patent: 6043133 (2000-03-01), Jang et al.
patent: 6194287 (2001-02-01), Jang
patent: 6440816 (2002-08-01), Farrow et al.
patent: 6939777 (2005-09-01), Ohto et al.
patent: 6979526 (2005-12-01), Ning
patent: 2006/0223200 (2006-10-01), Maruyama

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