Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-08-07
2003-03-04
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S672000
Reexamination Certificate
active
06528327
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device including a capacitor that has a capacitive insulating film of an insulating metal oxide and also relates to a method for fabricating the device.
Recently, as digital technology has been developed, the performance of various electronic units has been further enhanced to catch up with a steep rise in the amount of data to be processed or stored at a time. As a result, semiconductor devices included in a semiconductor chip for those electronic units have been rapidly downsized. Correspondingly, to integrate a dynamic RAM (Random Access Memory) more densely, a technique of using a material with a high dielectric constant (which will be herein referred to as a “high-dielectric-constant material”), instead of silicon dioxide or silicon nitride widely used, for a capacitive insulating film has been broadly researched and developed. Further, to implement a novel nonvolatile RAM that can operate at a low operating voltage and write and read data at a high speed, a ferroelectric film with spontaneous polarization properties has been vigorously researched and developed.
To realize a highly densely integrated memory with a storage capacity of several megabits using this high-dielectric-constant or ferroelectric material, a stacked memory cell should be used instead of a know planar memory cell.
In this case, the most essential task in fabricating a stacked memory cell is to prevent the interface between a contact plug and the lower electrode of a capacitor from being oxidized during an annealing process performed in an oxygen ambient for crystallizing the high-dielectric-constant or ferroelectric material.
Hereinafter, a known semiconductor memory device will be described with reference to the drawings.
FIG. 6
is a cross-sectional view illustrating a main portion processed in one process step of a first known method for fabricating a semiconductor memory device.
As shown in
FIG. 6
, a gate electrode
102
is formed over a semiconductor substrate
100
with a gate insulating film
101
interposed therebetween. An insulating sidewall
103
is formed on side faces of the gate electrode
102
. A doped layer
104
to be source/drain regions is defined in parts of the semiconductor substrate
100
below the gate electrode
102
to horizontally sandwich the gate electrode
102
therebetween. A transistor, including the gate electrode
102
, doped layer
104
, and so on, forms part of a semiconductor integrated circuit. And a passivation film
105
is deposited to cover the entire surface of the semiconductor substrate
100
including the semiconductor integrated circuit.
Further, as shown in
FIG. 6
, a contact hole
106
is formed in the passivation film
105
to reach the doped layer
104
. A conductive contact plug
107
is formed in the contact hole
106
. The contact plug
107
may be formed in the following manner. First, a conductor layers of polysilicon, tungsten, for example, is deposited over the entire surface of the semiconductor substrate
100
to fill in the contact hole
106
. After that, the conductor layer is etched back by a dry etching or CMP (chemical/mechanical polishing) process to remove the excessive parts of the conductor layer outside of the contact hole
106
. In this manner, the contact plug
107
can be formed out of the conductor layer in the contact hole
106
. In this case, unless the conductor layer and the passivation film
105
are etched at the same rate, it is impossible to make the upper surface of the contact plug
107
flush with that of passivation film
105
. However, in this etchback process, the etch rate of the material of the contact plug
107
is usually higher than that of the material of the passivation film
105
. Thus, the upper surface of the contact plug
107
will be lower than that of the passivation film
105
. As a result, a recess
108
having a wall standing vertically to the upper surface of the contact plug
107
is formed on the contact plug
107
.
Furthermore, as shown in
FIG. 6
, a lower electrode
109
is formed on the passivation film
105
, including the recess
108
, and connected to the contact plug
107
. The lower electrode
109
has a layered structure made up of: Ti layer; oxygen barrier layer of IrO
2
, Ir, or RuO
2
; and Pt layer that have been stacked in this order. A capacitive insulating film
110
made of an insulating metal oxide, e.g., high-dielectric-constant or ferroelectric material, is deposited on the lower electrode
109
. An upper electrode
111
is formed on the capacitive insulating film
110
. A capacitor
112
is made up of the lower electrode
109
, capacitive insulating film
110
, and upper electrode
111
.
However, in the structure shown in
FIG. 6
, the recess
108
exists on the contact plug
107
. In other words, a step
113
has been formed between the upper surfaces of the contact plug
107
and passivation film
105
. As a result, the following problems occur. Specifically, if the lower electrode
109
is formed by a sputtering process, for example, on the passivation film
105
including the recess
108
, the coverage of the lower electrode
109
will be poor due to the existence of the step
113
, i.e., the lower electrode
109
including the oxygen barrier layer partly thins. Thus, the ability of the lower electrode
109
at forming a barrier against oxygen (which will be herein referred to as “oxygen blockability”) deteriorates seriously. Accordingly, if an annealing process is performed in an oxygen ambient to crystallize the high-dielectric-constant or ferroelectric material that will be the capacitive insulating film
110
(which will be herein referred to as “annealing for crystallization”), oxygen reaches the surface of the contact plug
107
by way of the lower electrode
109
. As a result, the contact plug
107
is oxidized to cause contact failure. Also, disconnection might also occur because of the partial decrease in thickness of the lower electrode
109
.
In view of these problems, a countermeasure process, in which the wall of the recess is formed in a predetermined curved shape after the contact plug has been formed, was proposed in Japanese Laid-Open Publication No. 7-30077.
FIG. 7
is a cross-sectional view illustrating a main portion processed in one process step of a second known method for fabricating a semiconductor memory device as disclosed in Japanese Laid-Open Publication No. 7-30077. In
FIG. 7
, each member already shown in
FIG. 6
is identified by the same reference numeral and the description thereof will be omitted herein.
In the second example, the contact plug
107
is formed as in the first example, and then the passivation film
105
is wet-etched with an etchant including hydrofluoric acid, for example, using a masking pattern (not shown) covering a predetermined region. In this manner, the wall of the recess
108
is formed in a predetermined curved shape as shown in FIG.
7
. After that, the capacitor
112
is formed as in the first example.
However, the present inventors found that, it is also impossible in the second example to eliminate the above-mentioned problems completely, i.e., the contact plug
107
is oxidized during the annealing process for crystallizing the capacitive insulating film
110
to cause contact failures. That is to say, the wet etching process adopted for the second example disclosed in Japanese Laid-Open Publication No. 7-33077 is basically isotropic etching. Thus, as shown in
FIG. 7
, the passivation film
105
is wet-etched isotropically from the upper edge of the contact plug
107
as a start point. As a result, a first steep step
114
is unintentionally formed between the upper surface of the contact plug
107
and portion of the passivation film
105
near the contact plug
107
. In addition, the closer to the upper edge of the passivation film
105
, the closer to 90 degrees the angle formed by the recess wall with the upper surface of the passivation film
105
. Thus, another second steep step
115
is unintentionally formed ar
Fujii Eiji
Nagano Yoshihisa
Nasu Toru
Yasuoka Hajime
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Studebaker Donald R.
Tsai Jey
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