Fishing – trapping – and vermin destroying
Patent
1993-04-13
1994-08-09
Fourson, George
Fishing, trapping, and vermin destroying
437 48, 437 52, 437984, H01L 2128
Patent
active
053366280
ABSTRACT:
An improved integrated circuit and fabrication method for forming the improved integrated circuit is described. The method includes an anisotropic etching, without the use of either masks or photolithography, which removes insulating material from contact openings, but keeps insulating material on the sides of conductive layers, preventing inadvertent short circuits from the contact openings to the conductive layers. The maskless etching method makes it possible to avoid mask-wafer alignment errors and therefore frees designers to perfectly center contact openings within insulative regions without taking into account the surface area tolerances required under prior art fabrication methods. This freedom allows designers to design more highly integrated devices. The particular embodiments of the semiconductor integrated circuit may include floating gates (47) and control gates (52) covered with an upper oxide layer (53) on which electrical connection lines (11) have been installed.
REFERENCES:
patent: 4707717 (1987-11-01), Hirabayashi et al.
patent: 4768080 (1988-08-01), Sato
patent: 4851365 (1989-07-01), Jeuch et al.
patent: 4935380 (1990-06-01), Okumura
patent: 5107313 (1992-04-01), Kohda et al.
Commissariat a l''Energie Atomique
Fourson George
LandOfFree
Method for fabricating semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-215778