Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2003-06-10
2004-10-19
Lee, Hsien Ming (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
C438S687000, C438S791000
Reexamination Certificate
active
06806103
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed in general to the manufacture of integrated circuits, and, more specifically, to a method of fabricating semiconductor devices using processing steps that use an efficient plasma.
BACKGROUND OF THE INVENTION
The continuing miniaturization of semiconductor devices and the desire to produce faster semiconductor devices, has resulted in a shift toward the use of copper for making electrical interconnections in ultra-large scale integration circuits. Consider the fabrication of copper damascene interconnects, for example. Copper interconnect structures are formed by first depositing a dielectric layer on a semiconductor substrate, and then patterning and etching the dielectric layer to form an opening, such as a damascene structure. A refractory metal barrier, such a tantalum nitride or titanium nitride, and a copper seed layer are deposited in the opening. The opening is filled with copper, by electroplating onto the seed layer. The electrodeposited copper is then planarized by chemical mechanical polishing, leaving an inlaid copper structure.
The use of copper interconnects are not without difficulties, however. Copper atoms tend to readily diffuse into silicon-containing dielectric layers. The contamination by copper in unwanted locations can degrade or destroy the performance of active devices in integrated circuits. A dielectric barrier layer, such as silicon nitride or silicon carbide, deposited on the inlaid copper structure helps suppress copper migration and oxidation of the inlaid copper structure. The ability of the dielectric barrier to perform these functions and to adhere to copper is facilitated by depositing the dielectric on a uniformly prepared inlaid copper surface. Typically the inlaid copper structure is treated with a reducing plasma to remove copper oxides and contaminants, such as organic compounds, from the surface before depositing the dielectric barrier layer.
Failure of the dielectric barrier can result in significant additional costs to manufacture semiconductor devices, as well as diminish the perceived reliability of the semiconductor device by customers. At present, failure in the functioning of the dielectric barrier is only realized late in semiconductor device fabrication, or after the semiconductor device has been substantially completed. Often the detection of failure is by the observation of delamination of the dielectric barrier and any overlying structures from the inlaid copper structure, or by the failure of the semiconductor device to operate in the field. One reason why failures are detected late or after the fabrication process is because there is no practical method available to determine whether the plasma treatment of the copper inlaid surface was efficient for the entire copper surface.
Accordingly, what is needed in the art is a method of manufacturing semiconductor devices that includes the use of efficient plasma treatments.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a process of treating a target semiconductor surface. The process includes exposing a test surface to a plasma protocol and measuring chemical changes in discrete locations of the test surface. A target surface is prepared by exposing the target surface to the plasma protocol when a uniformity of the chemical changes are within a performance criterion of the plasma protocol.
In another embodiment, the present invention provides a semiconductor device made using the above-described process. A target surface is treated with a plasma protocol as described above and a dielectric layer is deposited on the target surface.
Yet another embodiment of the present invention is a method of manufacturing an integrated circuit. The method comprises forming an active device over a semiconductor substrate and forming an interconnect metal structure over the active device. Forming the interconnect metal structure includes treating said interconnect metal structure by the above-described process. Manufacturing the integrated circuit further includes connecting the interconnect metal structure to the active device to form an operative integrated circuit.
The foregoing has outlined preferred and alternative features of the present invention so that those of ordinary skill in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the scope of the invention.
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Junji Noguchi, Naofumi Ohashi, Jun-ichi Yasuda, Tomoko Jimbo, Hizuru Yamaguchi, Nobuo Owada, Ken-ichi Takeda and Kenji Hinode; “TDDB Improvement in CU Metallization Under Bias Stress”, IEEE 38th Annual Int'l Reliability Physics Symposium, San Jose, California 2000; pp. 339-343.
Kuan Yuji Richard
McKerrow Andrew John
Tsui Ting
Brady III W. James
Lee Hsien Ming
McLarty Peter K.
Telecky Frederick J.
Texas Instruments Incorporated
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