Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-08-03
2004-08-31
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S723000
Reexamination Certificate
active
06784109
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for fabricating semiconductor devices, and more particularly relates to a wiring forming method of semiconductor devices using porous material with low dielectric constant as intermetallic dielectric and using copper as conductor material.
2. Description of the Related Prior Arts
With respect to a wiring forming method of semiconductor devices using material with low dielectric constant, “Shingaku Giho; TECHNICAL REPORT OF IEICE, ED2000-136, SDM2000-118, ICD2000-72(2000-08), pp. 87-92” (reference 1) discloses the title “Technique for forming Cu dual damascene interconnects using low dielectric constant films”. Further, as a cleaning technique, “Gijutsu Joho Kyokai Shuppan (issued on Dec. 27, 2000) pp. 295-305” (reference 2) discloses the title “New material and process technique of the next generation of ULSI Interconnect”. Furthermore, as a resist ashing technique, there is a technique disclosed in “Japanese Published Unexamined Patent Application No. Hei 11-176818 (corresponding to U.S. Pat. No. 6,232,237) (references 3 and 4).
SUMMARY OF THE INVENTION
The present inventors have studied the following technique as a wiring forming method of semiconductor devices using material with low dielectric constant (hereinafter, called low—k dielectric) and copper. The method will be explained in accordance with the process diagram of FIG.
2
.
First, in (step
1
), a dielectric barrier film (e.g., an SiN film)
4
is deposited by CVD on a sample (an initial structure) having a copper layer
3
buried into the stacked-structure of a low-k film
1
and a silicon oxide (TEOS) layer
2
. In (step
2
), a low-k film
5
is coated thereon. In (step
3
), a mask material layer
6
(e.g., TEOS) is deposited thereon. In (step
4
), a material of the same kind of the dielectric barrier film
4
is deposited thereon as a mask material layer
7
. In (step
5
), a photoresist
8
is coated thereon to pattern a hole structure in the photoresist
8
. In (step
6
), the mask material layer
7
is dry-etched with the photoresist
8
as a mask to form a hole structure in the mask material layer
7
. In (step
7
), the photoresist
8
is removed. In (step
8
), a new photoresist
9
is coated to pattern a trench structure in the photoresist
9
. In (step
9
), the mask material layer
6
is dry-etched with the mask material layer
7
as a mask to form a hole structure in the mask material layer
6
, thereby providing a hard-mask made of the mask material layer
6
.
In (step
10
), the mask material layer
7
is etched with the photoresist
9
as a mask to form a trench structure in the mask material layer
7
, thereby providing a hard-mask made of the mask material layer
7
. In (step
11
), the low-k film
5
is subject to anisotropic dry etching with the mask material layer
6
as a mask to form a hole structure (a via hole)
10
. In (step
12
), the mask material layer
6
is dry-etched in a trench form with the mask material layer
7
as a mask. In this process, the photoresist
9
is removed at the same time.
In (step
13
), the low-k film
5
is subject to anisotropic dry etching with the mask material layers
7
and
6
as a mask to form a trench-structure recess
11
. In (step
14
), the dielectric barrier film
4
is removed by dry etching with the hole structure (the via hole)
10
formed in the low-k film
5
as a mask opening to form a hole structure. At the same time, the mask material layer
7
of the same material of the dielectric barrier film
4
is removed by dry etching. In (step
15
), to remove a polymer containing copper
12
deposited on the inner wall surface of the via hole
10
in the previous process, a fluorocarbon film
13
deposited on the inner wall surface of the trench-structure recess
11
, and a copper degraded layer
14
formed on the surface of the copper layer
3
, wet cleaning is performed using chemicals containing amine. In (step
16
), a Ta—TaN stacked film
15
is deposited by a sputtering method. In (step
17
), a copper layer
16
is deposited by the sputtering method.
In (step
18
), a copper film
17
is electrochemical deposited on the copper layer
16
deposited by sputtering in the previous process. In (step
19
), excess portions of the copper layer
16
, the copper film
17
, and the Ta—TaN stacked film
15
is removed by the CMP method (Chemical Mechanical Polishing). Finally, in (step
20
), the wet cleaning is performed to obtain a wiring completion sample of the first layer. The processes
1
to
20
are performed repeatedly to form interconnect.
In a high speed device, it is essential to use an insulating film with very low dielectric constant less than 2.5. Such an insulating film is entirely porous, that is, a low-k film like a sponge. The insulating film easily trap chemicals by the wet cleaning process and cannot be easily dried. The chemicals trapping of the porous low-k film is the principal problem.
The wiring method illustrated in
FIG. 2
using the porous low-k film has the wet cleaning process such as steps
15
and
20
. The porous low-k film traps chemicals in the wet cleaning process, so that moisture remains in the film. For example, when the above-mentioned method in reference 3 is used to omit two wet cleaning processes, the fluorocarbon film
13
can be removed by an H
2
O plasma processing. However, since the polymer containing copper
12
cannot be removed, the polymer containing copper
12
remains and diffuses in the porous low-k film to deteriorate the electric property of the porous low-k film. In the method of reference 3, as compared with the process of
FIG. 2
, since adhesion of the TEOS layer
2
to the dielectric barrier film
4
is poor, the layers are easily removed by thermal treatment.
As described above, due to chemicals trapping property, remaining of the polymer containing copper or the copper degraded layer, and low adhesion, wiring forming of the porous low-k film and copper is very difficult currently.
Accordingly, to solve the foregoing problems, an object of the present invention is to provide a method and apparatus capable of forming good wiring of a porous low-k film and copper.
The present inventors have found that the wet cleaning of the previous process
15
has, in addition to three effects of (1) removal of the fluorocarbon film
13
, (2) removal of the polymer containing copper
12
, and (3) removal of the copper degraded layer
14
, a fourth effect, (4) removal of fluorine included into the TEOS film in the etching process
14
by pure water cleaning in the wet cleaning process.
The above-mentioned method of reference 3 has no wet cleaning processes including the pure water cleaning at all, fluorine included into the TEOS film
6
in the etching process
14
remains. The present inventors have studied and found that the remaining fluorine lowers the adhesion of the dielectric barrier film
4
deposited on the TEOS film
6
in the second layer wiring forming process.
In other words, the present invention provides “A method for fabricating semiconductor devices comprising at least: a first step for forming a first insulating material layer (a dielectric barrier film) on a sample; a second step for forming on the first insulating material layer a second insulating material layer (a porous low-k film) with a dielectric constant less than 2.5; a third step for patterning the second insulating material layer by a plasma etching method; a fourth step for depositing a metal film on the second insulating material layer by a sputtering method; a fifth step for forming a copper layer on the metal film; and a sixth step for removing an unnecessary portion of the copper layer by Chemical Mechanical Polishing, wherein all the processes from the third to the fourth step are performed under drying process conditions, and a pure water treatment for cleaning the sample with pure water is provided after the sixth step”.
All the processes from the third step for patterning the second insulating material layer
Izawa Masaru
Kofuji Naoyuki
Chen Kin-Chan
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
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