Semiconductor device manufacturing: process – Forming tapered edges on substrate or adjacent layers
Patent
1999-06-08
2000-07-11
Bowers, Charles
Semiconductor device manufacturing: process
Forming tapered edges on substrate or adjacent layers
438666, 438667, 438668, 438672, 438673, H07L 2100
Patent
active
060872780
ABSTRACT:
There is provided a method for fabricating a semiconductor device, by which passivation layers are formed with good step coverage to prevent crack or void from being occurred in high aspect ratio of metallization layers and the time for performing the processes can be decreased to enhance the productability and the yield of the device. The method is performed as follows. Over a substrate having completed metallization layers, an oxide layer is formed as a first passivation layer by high-density plasma chemical vapor deposition (HDP-CVD). On the HDP-CVD oxide layer, a nitride layer is formed as a second passivation layer by plasma enhanced chemical vapor deposition (PECVD) or HDP-CVD.
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Redeker Fred C et al., "Plasma Source For HDP-CVD Chamber", Patent Abstracts of Japan, Application No. 10028509, filed Feb. 10, 1998.
Kim Han Min
Kim Sun Oo
Bowers Charles
Hyundai Electronics Industries Co,. Ltd.
Kilday Lisa
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