Method for fabricating semiconductor device with vertical gate

Details Method for fabricating semiconductor device with vertical gate Method for fabricating semiconductor device with vertical gate

2011-07-19

2011-07-19

Richards, N Drew (Department: 2895)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S239000, C438S243000, C438S253000, C438S268000, C438S270000, C257S296000, C257S302000, C257S306000, C257S315000, C257S329000, C257SE21410

Reexamination Certificate

active

07981764

ABSTRACT:
A method for fabricating a semiconductor device includes: forming a stack structure including pillar regions whose upper portion has a wider width than a lower portion over a substrate, the lower portion including at least a conductive layer; forming a gate insulation layer on sidewalls of the pillar regions; forming active pillars to gap-fill the pillar regions; and forming vertical gates that serve as both gate electrode and word lines by selectively etching the conductive layer.

REFERENCES:
patent: 5578850 (1996-11-01), Fitch et al.
patent: 2009/0108340 (2009-04-01), Seo
patent: 1020060041415 (2006-05-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Jan. 5, 2011.

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