Method for fabricating semiconductor device isolation region usi

Details Method for fabricating semiconductor device isolation region usi Method for fabricating semiconductor device isolation region usi

1995-06-05

1997-12-09

Fourson, George

Fishing, trapping, and vermin destroying

1566361, H01L 2176

Patent

active

056960204

ABSTRACT:
Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxide film and the silicon oxide film and removing the polysilicon film only the inactive region; performing a thermal oxidation to form a field oxide film on the inactive region; and sequentially removing the isolating layer and the polysilicon film formed on the active region. Because the active region is defined using an insulator-filled shallow trench before performing thermal oxidation, no oxygen is penetrated into the active region during the thermal oxidation, whereby a field oxide film can be formed without occurrence of a Bird's beak.

REFERENCES:
patent: 5002898 (1991-03-01), Fritzinger et al.
patent: 5130268 (1992-07-01), Liou et al.
patent: 5371036 (1994-12-01), Lur et al.
patent: 5432118 (1995-07-01), Orlowski et al.
Shimizu, N., et al, "A Poly Buffered LOCOS Process for 256 Mbit DRAM Cells", IEDM '92, pp. 279-282.

Affiliated with

Also associated with

Rating

Method for fabricating semiconductor device isolation region usi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating semiconductor device isolation region usi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor device isolation region usi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1607297