Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2006-05-09
2006-05-09
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S445000, C257S301000
Reexamination Certificate
active
07041573
ABSTRACT:
Disclosed is a method for fabricating a semiconductor device capable of preventing a depth of a plurality of moats M from getting deeper as preventing lowering a threshold voltage by forming a round shape of a top corner of a trench. Particularly, the method includes the steps of: forming a pad pattern by sequentially stacking a pad oxide layer and a pad nitride layer on a substrate; forming a trench by etching process to an exposed surface of the substrate by using the pad pattern as a mask; filling an insulation layer for isolating device elements filled into the trench; removing the pad nitride layer; performing a pre-cleaning process for removing the pad oxide layer; selectively recessing the surface of the substrate to remove a plurality of moats M taken place after removing the pad oxide layer; and forming a screen oxide layer on the surface of the substrate.
REFERENCES:
patent: 6037238 (2000-03-01), Chang et al.
patent: 6255176 (2001-07-01), Kim et al.
patent: 6391793 (2002-05-01), Lee et al.
patent: 6784077 (2004-08-01), Lin et al.
Blakely & Sokoloff, Taylor & Zafman
Hynix / Semiconductor Inc.
Le Dung A.
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