Fishing – trapping – and vermin destroying
Patent
1993-07-23
1995-01-31
Thomas, Tom
Fishing, trapping, and vermin destroying
437 47, 437 60, 437919, H01L 2170
Patent
active
053858581
ABSTRACT:
A method for fabricating a semiconductor device includes the steps of forming a MIS transistor, a contact hole, a sidewall insulating film, a first electrode, a dielectric film and a second electrode. The contact hole is formed by depositing a lower and an upper insulating film to cover the MIS transistor and selectively etching the insulating films to expose an upper surface of one of impurity diffusion layers serving as source/drain regions. The sidewall insulating film is formed by depositing an insulating material film using a material whose etching-back rate is different from that of the material for the upper insulating layer. The etching rate of the upper insulating layer is higher than that for the insulating material film. The etching-back under this etching condition results in the formation of the sidewall insulating film that projects upwardly from the surface of the upper insulating layer. With this configuration, it is possible to increase a surface area of the electrodes of a capacitor.
REFERENCES:
patent: 5023683 (1991-06-01), Yamada
patent: 5071783 (1991-12-01), Taguchi et al.
patent: 5084405 (1992-01-01), Fazan et al.
patent: 5162248 (1992-11-01), Dennison et al.
NEC Corporation
Thomas Tom
LandOfFree
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