Method for fabricating semiconductor device having CMOS structur

Details Method for fabricating semiconductor device having CMOS structur Method for fabricating semiconductor device having CMOS structur

1996-10-30

1997-11-25

Niebling, John

Fishing, trapping, and vermin destroying

437 34, 437200, H01L 2170

Patent

active

056912250

ABSTRACT:
A semiconductor device having a CMOS structure having a low resistivity silicide layer in a source/drain region is fabricated. To realize silicide formation for resistivity reduction of the n-type source/drain region, an impurity-free silicon layer is formed thereon before forming a high melting point metal silicide layer. For the n-type source/drain region, ion implantation is made through the silicon layer. It is thus possible to obtain a shallow junction of the p-type source/drain region, prevent ion implantation time increase and obtain quick fabrication without reducing the ion implantation energy.

REFERENCES:
Tohru Ogami et al, "A Novel Salicide Process (SEDAM) for Sub-Quarter Micron CMOS Devices", 1994 IEDM Technical Digest, pp. 687-690.
T. Ohguro et al, "The Influence of Oxygen at Epitaxial Si/Si Substrate Interface for 0.1.mu.m Epitaxial Si Channel N-MOSFETs Grown by UHV-CVD", 1995 Symposium on VLSI Technology Digest of Technical Papers, pp.21-22.

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