Fishing – trapping – and vermin destroying
Patent
1995-01-04
1997-07-29
Quach, T. N.
Fishing, trapping, and vermin destroying
437 41GS, 437 57, 437193, H01L 21283
Patent
active
056521839
ABSTRACT:
A method for fabricating a semiconductor device which includes a metal silicide film for electrically connecting a first silicon region containing a p-type impurity with a second silicon region containing an n-type impurity is disclosed. The method includes the step of depositing the metal silicide film so as to contain excessive silicon. Such excessive silicon is precipitated in silicide grain boundaries in the metal silicide film and thus makes a diffusion path of impurities along the silicide grain boundaries discontinuous.
REFERENCES:
patent: 4443930 (1984-04-01), Hwang et al.
patent: 4640004 (1987-02-01), Thomas et al.
patent: 4782033 (1988-11-01), Gierisch et al.
patent: 4786611 (1988-11-01), Pfiester
patent: 4912542 (1990-03-01), Suguro
patent: 4920071 (1990-04-01), Thomas
patent: 5100811 (1992-03-01), Winnerl et al.
patent: 5162884 (1992-11-01), Lion et al.
patent: 5190886 (1993-03-01), Asahina
patent: 5268590 (1993-12-01), Pfiester et al.
patent: 5341014 (1994-08-01), Fujii et al.
patent: 5355010 (1994-10-01), Fujii et al.
patent: 5459101 (1995-10-01), Fujii et al.
C.L. Chu et al., "Technology Limitations for N.sup.30 /P.sup.30 Polycide Gate CMOS due to Lateral Dopant Diffusion in Silicide/Polysilicon Layers", IEEE Electron Device Letters, vol. 12, No. 12, Dec. 1991.
T. Fujii et al., "Dual (n.sup.30 /p.sup.30) Polycide Gate Technology using Si-rich WSix to Exterminate Lateral Dopant Diffusion", 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 117-118, 7-9 Jun. 1994.
L. C. Parrillo et al., "A Fine-Line CMOS Technology That Uses P.sup.30 -Polysilicon/Silicide Gates for NMOS and PMOS Devices", IEEE IEDM Technical Digests, pp. 418-422, Dec. 1984.
Matsushita Electric - Industrial Co., Ltd.
Quach T. N.
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