Method for fabricating semiconductor device

Details Method for fabricating semiconductor device Method for fabricating semiconductor device

1998-12-08

2001-05-15

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S637000, C438S710000, C438S734000, C438S738000, C430S329000, C134S001200

Reexamination Certificate

active

06232237

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more particularly relates to a method including the process step of ashing a resist mask.
As the number of semiconductor devices integrated on a single wafer has been tremendously increased in LSI's, for example, it has become more and more necessary to form interconnection structures having an even larger number of layers stacked therein with a higher and higher density. The upperlevel portion of such a multilevel interconnection structure has a larger step. Thus, if a fine-line wiring pattern is formed over such a step, then various problems such as disconnection or breaking of interconnections possibly happen. Accordingly, in order to form a multilevel interconnection structure more easily, the surface of the interlevel dielectric thereof should be planarized. Various techniques have been researched and developed to planarize the surface of an interlevel dielectric. Among other things, a spin-on-glass (SOG) technique is widely used because the process can be carried out easily. In accordance with the SOG technique, a liquid insulator made of an inorganic or organic material is applied onto the stepped surface of a semiconductor substrate so as to form an interlevel dielectric with a planarized surface.
On the other hand, as an interconnection structure has been formed with a higher and higher density, wiring capacitance thereof has also increased. Wiring capacitance is one of the factors increasing signal propagation delay, power consumption, crosstalk and the like, and thus seriously affects the operating characteristics of a semiconductor device. In order to reduce wiring capacitance, an insulator having a low relative dielectric constant is required.
Silicon dioxide (SiO
2
), formed by thermal oxidation or chemical vapor deposition (CVD), is a typical insulator currently used. The relative dielectric constant of SiO
2
is in the range from about 3.9 to about 5.0. However, this relative dielectric constant is not low enough to reduce the wiring capacitance satisfactorily. Accordingly, a material having an even lower dielectric constant is required. Various techniques have been proposed to form an insulator film having a low dielectric constant. The SOG technique is also used widely for such a purpose.
In recent years, hydrogen silsesquioxane (HSQ) is the object of attention as a material for an insulator film having a relative dielectric constant as low as about 3.0. HSQ is described in detail in an article by Valance et al. (1992 VMIC Conference) and in an article by Plamanick et al. (1993 VMIC Conference). As shown in
FIG. 1
, HSQ has a cubic polymer structure and is expressed by a general formula (HSiO
1.5
)
2n
(where n=2 to 8). An HSQ layer can be formed by the SOG technique. Specifically, a substrate is spin-coated with HSQ and baked at 400° C. within a nitrogen ambient. As a result, polymers are bonded to each other, thereby forming an HSQ layer.
Next, a conventional method for fabricating a semiconductor device using HSQ will be described with reference to
FIGS. 2A through 2H
. In the following example, a prior-art semiconductor device having a two-layer interconnection structure will be exemplified for the sake of simplicity.
First, as shown in
FIG. 2A
, a structure including a first interconnection layer
3
is formed on an insulator layer
2
on a semiconductor substrate
1
. Over the first interconnection layer
3
, a first silicon dioxide layer
4
is deposited in accordance with a thin film deposition technique such as CVD.
Next, as shown in
FIG. 2B
, an HSQ layer
5
is formed by the SOG technique. Then, as shown in
FIG. 2C
, a second silicon dioxide layer
6
is formed over the HSQ layer
5
by a plasma CVD technique or the like.
Subsequently, as shown in
FIG. 2D
, a resist mask
7
is formed over an interlevel dielectric film having a three-layer structure formed in this manner. Thereafter, a predetermined part of the resist mask
7
is removed by a known photolithography technique to provide an opening in the resist mask
7
. Then, as shown in
FIG. 2E
, part of the three-layer interlevel dielectric film, which part is not covered with the resist mask
7
, is removed by a dry etching technique so as to form a via hole
8
in the interlevel dielectric film.
Next, as shown in
FIG. 2F
, the resist mask
7
is ashed and removed by using oxygen (O
2
) plasma
15
. During this process step of ashing the resist mask
7
using the O
2
plasma
15
, the part of the three-layer interlevel dielectric film, where the via hole
8
is formed, is exposed to the O
2
plasma
15
. The silicon dioxide layers
4
and
6
, which have been formed by the plasma CVD technique, are highly resistant to the O
2
plasma
15
and are not affected during this process. By contrast, the HSQ layer
5
has poor resistance to the O
2
plasma
15
, and is easily oxidized. As a result, the components of the film are dissolved to deform and dent the film or form an altered layer
16
(i.e., degraded region) as shown in FIG.
2
G. The altered layer
16
is a film containing a lot of water. In such a state, if a plug
10
is made of tungsten or the like in the via hole
8
to form a second interconnection layer
11
, then water is ejected from the altered layer
16
during subsequent process steps. The ejection of water makes plugs
10
and interconnections
11
defective, and contributes to disconnection thereof and increase in resistance (see FIG.
2
H).
The fact that an HSQ layer is altered and the content of water is increased as a result of the oxygen plasma is disclosed, for example, in an article by B. T. Ahlburn, G. A. Brown, T. R. Seha and T. F. Zoes, “Hydrogen Silsesquioxane-based Flowable Oxide as an Element in the Interlevel Dielectric for Sub 0.5 Micron ULSI Circuits”, 1995 Proceedings Dielectrics for VLSI/ULSI Multilevel Interconnection Conference, p.36). According to Ahlburn et al., Si—H bonds in an HSQ layer are oxidized by oxygen plasma to produce Si—O bonds and H—OH bonds, and OH groups constitute water in the film. In addition, oxidation shrinks the film or deforms and dents the film.
In fabricating a semiconductor device using the HSQ material in the above-described manner, during the removal of a resist mask by an ashing technique using oxygen plasma, the oxygen plasma adversely deforms and dents the HSQ material exposed or alters the HSQ film into a highly hygroscopic film containing a lot of water. Moreover, during a subsequent process step of forming interconnections, gases such as water vapor disadvantageously come out of the altered layer to form defective interconnections.
In accordance with a method for preventing the HSQ layer from being degraded during the process step of ashing and removing the resist mask, a structure, in which the HSQ layer is not exposed inside the via hole over the pattern of the first interconnection layer, is formed by etching back the HSQ layer so as not to leave the HSQ layer over the pattern of the first interconnection layer. This etchback method, however, has various problems. For example, it is difficult to accurately control such a process; the number of required process steps increases; and wiring capacitance cannot be sufficiently reduced because the fringe components of the capacitance cannot be reduced during the formation of a film out of a material having a low dielectric constant.
SUMMARY OF THE INVENTION
In view of the above-described problems, the present invention relates to a method for fabricating a semiconductor device in such a manner that resist ashing does not adversely affect an exposed surface of an insulator film.
In accordance with an exemplary embodiment, the present invention relates to a method for fabricating a semiconductor device, comprising the steps of: a) forming an insulator film having Si—H bonds; b) forming a resist mask over a selected region of the insulator film; c) etching a part of the insulator film that is not covered with the resist mask, thereby forming a reces

Affiliated with

Also associated with

Rating

Method for fabricating semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2514256